74 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_enable()  local
85 	channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
89 	writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
90 	mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);  in mchp_core_pwm_enable()
91 	mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;  in mchp_core_pwm_enable()
98 	if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))  in mchp_core_pwm_enable()
99 		mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);  in mchp_core_pwm_enable()
102 static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,  in mchp_core_pwm_wait_for_sync_update()  argument
113 	if (mchp_core_pwm->sync_update_mask & (1 << channel)) {  in mchp_core_pwm_wait_for_sync_update()
118 		remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,  in mchp_core_pwm_wait_for_sync_update()
155 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply_duty()  local
181 	writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
182 	writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
277 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply_locked()  local
294 	clk_rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_apply_locked()
311 	period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);  in mchp_core_pwm_apply_locked()
317 		hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
318 		hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
349 		writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
350 		writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
363 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply()  local
366 	mutex_lock(&mchp_core_pwm->lock);  in mchp_core_pwm_apply()
368 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_apply()
372 	mutex_unlock(&mchp_core_pwm->lock);  in mchp_core_pwm_apply()
380 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_get_state()  local
385 	mutex_lock(&mchp_core_pwm->lock);  in mchp_core_pwm_get_state()
387 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_get_state()
389 	if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))  in mchp_core_pwm_get_state()
394 	rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_get_state()
409 	prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_get_state()
410 	period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_get_state()
416 	posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
417 	negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
419 	mutex_unlock(&mchp_core_pwm->lock);  in mchp_core_pwm_get_state()
451 	struct mchp_core_pwm_chip *mchp_core_pwm;  in mchp_core_pwm_probe()  local
455 	mchp_core_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_core_pwm), GFP_KERNEL);  in mchp_core_pwm_probe()
456 	if (!mchp_core_pwm)  in mchp_core_pwm_probe()
459 	mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);  in mchp_core_pwm_probe()
460 	if (IS_ERR(mchp_core_pwm->base))  in mchp_core_pwm_probe()
461 		return PTR_ERR(mchp_core_pwm->base);  in mchp_core_pwm_probe()
463 	mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in mchp_core_pwm_probe()
464 	if (IS_ERR(mchp_core_pwm->clk))  in mchp_core_pwm_probe()
465 		return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),  in mchp_core_pwm_probe()
469 				 &mchp_core_pwm->sync_update_mask))  in mchp_core_pwm_probe()
470 		mchp_core_pwm->sync_update_mask = 0;  in mchp_core_pwm_probe()
472 	mutex_init(&mchp_core_pwm->lock);  in mchp_core_pwm_probe()
474 	mchp_core_pwm->chip.dev = &pdev->dev;  in mchp_core_pwm_probe()
475 	mchp_core_pwm->chip.ops = &mchp_core_pwm_ops;  in mchp_core_pwm_probe()
476 	mchp_core_pwm->chip.npwm = 16;  in mchp_core_pwm_probe()
478 	mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));  in mchp_core_pwm_probe()
479 	mchp_core_pwm->channel_enabled |=  in mchp_core_pwm_probe()
480 		readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;  in mchp_core_pwm_probe()
486 	writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);  in mchp_core_pwm_probe()
487 	mchp_core_pwm->update_timestamp = ktime_get();  in mchp_core_pwm_probe()
489 	ret = devm_pwmchip_add(&pdev->dev, &mchp_core_pwm->chip);  in mchp_core_pwm_probe()