17  *   As setting the period/duty cycle takes 4 register writes, there is a window
18  *   in which this races against the start of a new period.
23  *   period. Therefore to get a 0% waveform, the output is set the max high/low
25  *   If the duty cycle is 0%, and the requested period is less than the
26  *   available period resolution, this will manifest as a ~100% waveform (with
28  * - The PWM period is set for the whole IP block not per channel. The driver
29  *   will only change the period if no other PWM output is enabled.
60 	struct mutex lock; /* protects the shared period */
72 				 bool enable, u64 period)  in mchp_core_pwm_enable()  argument
95 	 * applied to the waveform at the beginning of the next period.  in mchp_core_pwm_enable()
99 		mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);  in mchp_core_pwm_enable()
110 	 * once the current period has ended.  in mchp_core_pwm_wait_for_sync_update()
140 	 * Calculate the duty cycle in multiples of the prescaled period:  in mchp_core_pwm_calc_duty()
191 	 * Calculate the period cycles and prescale values.  in mchp_core_pwm_calc_period()
192 	 * The registers are each 8 bits wide & multiplied to compute the period  in mchp_core_pwm_calc_period()
195 	 * period = -------------------------------------  in mchp_core_pwm_calc_period()
197 	 * so the maximum period that can be generated is 0x10000 times the  in mchp_core_pwm_calc_period()
198 	 * period of the input clock.  in mchp_core_pwm_calc_period()
202 	 * of the clock period attainable is (0xff + 1) * (0xfe + 1) = 0xff00  in mchp_core_pwm_calc_period()
207 	 * It's therefore not possible to set a period lower than 1/clk_rate, so  in mchp_core_pwm_calc_period()
208 	 * if tmp is 0, abort. Without aborting, we will set a period that is  in mchp_core_pwm_calc_period()
212 	tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);  in mchp_core_pwm_calc_period()
224 	 * is as finegrain as possible, while also keeping the period less than  in mchp_core_pwm_calc_period()
231 	 * Integer division will ensure a round down, so the period will thereby  in mchp_core_pwm_calc_period()
238 	 * As we must produce a period less than that requested, and for the  in mchp_core_pwm_calc_period()
249 	 *                period * clk_rate  in mchp_core_pwm_calc_period()
254 	 *  period * clk_rate  in mchp_core_pwm_calc_period()
262 	 *                      period * clk_rate  in mchp_core_pwm_calc_period()
285 		mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);  in mchp_core_pwm_apply_locked()
306 	 * As all the channels share the same period, do not allow it to be  in mchp_core_pwm_apply_locked()
308 	 * If the period is locked, it may not be possible to use a period  in mchp_core_pwm_apply_locked()
329 		 * The period is locked and we cannot change this, so we abort.  in mchp_core_pwm_apply_locked()
341 	 * Because the period is not per channel, it is possible that the  in mchp_core_pwm_apply_locked()
342 	 * requested duty cycle is longer than the period, in which case cap it  in mchp_core_pwm_apply_locked()
343 	 * to the period, IOW a 100% duty cycle.  in mchp_core_pwm_apply_locked()
355 	mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);  in mchp_core_pwm_apply_locked()
397 	 * Calculating the period:  in mchp_core_pwm_get_state()
398 	 * The registers are each 8 bits wide & multiplied to compute the period  in mchp_core_pwm_get_state()
401 	 * period = -------------------------------------  in mchp_core_pwm_get_state()
412 	state->period = (period_steps + 1) * (prescale + 1);  in mchp_core_pwm_get_state()
413 	state->period *= NSEC_PER_SEC;  in mchp_core_pwm_get_state()
414 	state->period = DIV64_U64_ROUND_UP(state->period, rate);  in mchp_core_pwm_get_state()
422 		state->duty_cycle = state->period;  in mchp_core_pwm_get_state()
423 		state->period *= 2;  in mchp_core_pwm_get_state()