1 // SPDX-License-Identifier: GPL-2.0
7  *          Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
10  * - Upon disabling a channel, the currently running
69  * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
74 	u32 buff = readl(priv->base + offset);  in keembay_pwm_update_bits()
77 	writel(buff, priv->base + offset);  in keembay_pwm_update_bits()
96 	unsigned long long high, low;  in keembay_pwm_get_state()  local
100 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_get_state()
103 	highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
105 		state->enabled = true;  in keembay_pwm_get_state()
107 		state->enabled = false;  in keembay_pwm_get_state()
110 	highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
111 	low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;  in keembay_pwm_get_state()
113 	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);  in keembay_pwm_get_state()
114 	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);  in keembay_pwm_get_state()
115 	state->polarity = PWM_POLARITY_NORMAL;  in keembay_pwm_get_state()
128 	u16 high, low;  in keembay_pwm_apply()  local
130 	if (state->polarity != PWM_POLARITY_NORMAL)  in keembay_pwm_apply()
131 		return -EINVAL;  in keembay_pwm_apply()
135 	 * low time as 0 at (30:16), which is in terms of clock cycles.  in keembay_pwm_apply()
138 				KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
142 	if (!state->enabled) {  in keembay_pwm_apply()
144 			keembay_pwm_disable(priv, pwm->hwpwm);  in keembay_pwm_apply()
150 	 * register contain the high time and low time of waveform accordingly.  in keembay_pwm_apply()
154 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_apply()
155 	div = clk_rate * state->duty_cycle;  in keembay_pwm_apply()
158 		return -ERANGE;  in keembay_pwm_apply()
161 	div = clk_rate * state->period;  in keembay_pwm_apply()
163 	div = div - high;  in keembay_pwm_apply()
165 		return -ERANGE;  in keembay_pwm_apply()
167 	low = div;  in keembay_pwm_apply()
170 		    FIELD_PREP(KMB_PWM_LOW_MASK, low);  in keembay_pwm_apply()
172 	writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
174 	if (state->enabled && !current_state.enabled)  in keembay_pwm_apply()
175 		keembay_pwm_enable(priv, pwm->hwpwm);  in keembay_pwm_apply()
188 	struct device *dev = &pdev->dev;  in keembay_pwm_probe()
194 		return -ENOMEM;  in keembay_pwm_probe()
196 	priv->clk = devm_clk_get(dev, NULL);  in keembay_pwm_probe()
197 	if (IS_ERR(priv->clk))  in keembay_pwm_probe()
198 		return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");  in keembay_pwm_probe()
200 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in keembay_pwm_probe()
201 	if (IS_ERR(priv->base))  in keembay_pwm_probe()
202 		return PTR_ERR(priv->base);  in keembay_pwm_probe()
204 	ret = keembay_clk_enable(dev, priv->clk);  in keembay_pwm_probe()
208 	priv->chip.dev = dev;  in keembay_pwm_probe()
209 	priv->chip.ops = &keembay_pwm_ops;  in keembay_pwm_probe()
210 	priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;  in keembay_pwm_probe()
212 	ret = devm_pwmchip_add(dev, &priv->chip);  in keembay_pwm_probe()
220 	{ .compatible = "intel,keembay-pwm" },
228 		.name = "pwm-keembay",
234 MODULE_ALIAS("platform:pwm-keembay");