Lines Matching +full:0 +full:x390000
27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
65 #define OCP_CTRL_ENABLE BIT(0)
73 #define OCP_STATUS_IN_SYNC BIT(0)
76 #define OCP_SELECT_CLK_NONE 0
77 #define OCP_SELECT_CLK_REG 0xfe
95 #define TOD_CTRL_ENABLE BIT(0)
96 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
99 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
130 #define PPS_STATUS_FILTER_ERR BIT(0)
153 #define IRIG_M_CTRL_ENABLE BIT(0)
164 #define IRIG_S_CTRL_ENABLE BIT(0)
174 #define DCF_M_CTRL_ENABLE BIT(0)
184 #define DCF_S_CTRL_ENABLE BIT(0)
218 #define FREQ_STATUS_MASK GENMASK(23, 0)
276 #define OCP_CAP_BASIC BIT(0)
357 #define OCP_REQ_TIMESTAMP BIT(0)
407 { EEPROM_ENTRY(0x43, board_id) },
408 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
413 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
414 { EEPROM_ENTRY(0x200 + 0x63, serial) },
442 * 0: PPS (TS5)
471 .offset = 0x01000000, .size = 0x10000,
475 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
477 .index = 0,
484 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
493 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
502 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
511 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
521 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
529 OCP_EXT_RESOURCE(signal_out[0]),
530 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
539 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
548 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
557 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
566 .offset = 0x01030000, .size = 0x10000,
570 .offset = 0x01040000, .size = 0x10000,
574 .offset = 0x01050000, .size = 0x10000,
578 .offset = 0x01070000, .size = 0x10000,
582 .offset = 0x01080000, .size = 0x10000,
586 .offset = 0x01090000, .size = 0x10000,
590 .offset = 0x010A0000, .size = 0x10000,
594 .offset = 0x010B0000, .size = 0x10000,
598 .offset = 0x00020000, .size = 0x1000,
602 .offset = 0x00130000, .size = 0x1000,
606 .offset = 0x00140000, .size = 0x1000,
610 .offset = 0x00220000, .size = 0x1000,
614 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
622 { I2C_BOARD_INFO("24c02", 0x50) },
623 { I2C_BOARD_INFO("24mac402", 0x58),
631 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
638 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
645 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
652 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
656 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
658 .name = "xilinx_spi", .pci_offset = 0,
672 OCP_MEM_RESOURCE(freq_in[0]),
673 .offset = 0x01200000, .size = 0x10000,
677 .offset = 0x01210000, .size = 0x10000,
681 .offset = 0x01220000, .size = 0x10000,
685 .offset = 0x01230000, .size = 0x10000,
706 .offset = 0x01000000, .size = 0x10000,
710 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
717 .offset = 0x003C0000, .size = 0x1000,
722 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
724 .index = 0,
731 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
740 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
749 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
758 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
768 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
777 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
779 .name = "spi_altera", .pci_offset = 0,
792 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
802 I2C_BOARD_INFO("24c08", 0x50),
809 .offset = 0x00190000, .irq_vec = 7,
816 .offset = 0x210000, .size = 0x1000,
841 { .name = "NONE", .value = 0 },
848 { .name = "REGS", .value = 0xfe },
849 { .name = "EXT", .value = 0xff },
855 #define SMA_SELECT_MASK GENMASK(14, 0)
858 { .name = "10Mhz", .value = 0x0000 },
859 { .name = "PPS1", .value = 0x0001 },
860 { .name = "PPS2", .value = 0x0002 },
861 { .name = "TS1", .value = 0x0004 },
862 { .name = "TS2", .value = 0x0008 },
863 { .name = "IRIG", .value = 0x0010 },
864 { .name = "DCF", .value = 0x0020 },
865 { .name = "TS3", .value = 0x0040 },
866 { .name = "TS4", .value = 0x0080 },
867 { .name = "FREQ1", .value = 0x0100 },
868 { .name = "FREQ2", .value = 0x0200 },
869 { .name = "FREQ3", .value = 0x0400 },
870 { .name = "FREQ4", .value = 0x0800 },
876 { .name = "10Mhz", .value = 0x0000 },
877 { .name = "PHC", .value = 0x0001 },
878 { .name = "MAC", .value = 0x0002 },
879 { .name = "GNSS1", .value = 0x0004 },
880 { .name = "GNSS2", .value = 0x0008 },
881 { .name = "IRIG", .value = 0x0010 },
882 { .name = "DCF", .value = 0x0020 },
883 { .name = "GEN1", .value = 0x0040 },
884 { .name = "GEN2", .value = 0x0080 },
885 { .name = "GEN3", .value = 0x0100 },
886 { .name = "GEN4", .value = 0x0200 },
887 { .name = "GND", .value = 0x2000 },
888 { .name = "VCC", .value = 0x4000 },
893 { .name = "PPS1", .value = 0x0001 },
894 { .name = "10Mhz", .value = 0x0008 },
899 { .name = "PHC", .value = 0x0002 },
900 { .name = "GNSS", .value = 0x0004 },
901 { .name = "10Mhz", .value = 0x0010 },
942 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_name_from_val()
954 for (i = 0; tbl[i].name; i++) { in ptp_ocp_select_val_from_name()
968 count = 0; in ptp_ocp_select_table_show()
969 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_table_show()
989 for (i = 0; i < 100; i++) { in __ptp_ocp_gettime_locked()
1008 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; in __ptp_ocp_gettime_locked()
1058 return 0; in ptp_ocp_settime()
1105 return 0; in ptp_ocp_adjtime()
1108 sign = delta_ns < 0 ? BIT(31) : 0; in ptp_ocp_adjtime()
1115 return 0; in ptp_ocp_adjtime()
1121 if (scaled_ppm == 0) in ptp_ocp_null_adjfine()
1122 return 0; in ptp_ocp_null_adjfine()
1130 return 0; in ptp_ocp_null_getmaxphase()
1152 case 0: in ptp_ocp_enable()
1178 case 0: in ptp_ocp_enable()
1183 rq->perout.period.nsec != 0)) in ptp_ocp_enable()
1185 return 0; in ptp_ocp_enable()
1222 return 0; in ptp_ocp_verify()
1224 /* channel 0 is 1PPS from PHC. in ptp_ocp_verify()
1264 iowrite32(0, &bp->reg->drift_ns); in __ptp_ocp_clear_drift_locked()
1311 bp->gnss_lost = 0; in ptp_ocp_watchdog()
1361 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ in ptp_ocp_init_clock()
1362 iowrite32(0x2000, &bp->reg->servo_offset_p); in ptp_ocp_init_clock()
1363 iowrite32(0x1000, &bp->reg->servo_offset_i); in ptp_ocp_init_clock()
1364 iowrite32(0, &bp->reg->servo_drift_p); in ptp_ocp_init_clock()
1365 iowrite32(0, &bp->reg->servo_drift_i); in ptp_ocp_init_clock()
1371 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { in ptp_ocp_init_clock()
1386 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); in ptp_ocp_init_clock()
1390 return 0; in ptp_ocp_init_clock()
1442 return 0; in ptp_ocp_nvmem_match()
1447 return 0; in ptp_ocp_nvmem_match()
1541 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1549 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1558 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1562 crc = crc16(0xffff, &fw->data[offset], length); in ptp_ocp_devlink_fw_image()
1566 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1573 return 0; in ptp_ocp_devlink_fw_image()
1592 off = 0; in ptp_ocp_devlink_flash()
1637 NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1642 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1666 return 0; in ptp_ocp_devlink_info_get()
1680 return 0; in ptp_ocp_devlink_info_get()
1701 start = pci_resource_start(bp->pdev, 0) + r->offset; in ptp_ocp_get_mem()
1729 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_register_spi()
1730 ptp_ocp_set_mem_resource(&res[0], start, r->size); in ptp_ocp_register_spi()
1745 return 0; in ptp_ocp_register_spi()
1756 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_i2c_bus()
1757 ptp_ocp_set_mem_resource(&res[0], start, r->size); in ptp_ocp_i2c_bus()
1779 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, in ptp_ocp_register_i2c()
1793 return 0; in ptp_ocp_register_i2c()
1813 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_irq()
1814 iowrite32(0, ®->enable); in ptp_ocp_signal_irq()
1818 iowrite32(0, ®->intr); /* ack interrupt */ in ptp_ocp_signal_irq()
1832 return 0; in ptp_ocp_signal_set()
1860 return 0; in ptp_ocp_signal_set()
1872 return 0; in ptp_ocp_signal_from_perout()
1898 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_enable()
1899 iowrite32(0, ®->enable); in ptp_ocp_signal_enable()
1902 return 0; in ptp_ocp_signal_enable()
1917 iowrite32(0, ®->repeat_count); in ptp_ocp_signal_enable()
1919 iowrite32(0, ®->intr); /* clear interrupt state */ in ptp_ocp_signal_enable()
1925 return 0; in ptp_ocp_signal_enable()
1942 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) in ptp_ocp_ts_irq()
1978 if ((!!old_map ^ !!bp->pps_req_map) == 0) in ptp_ocp_ts_enable()
1979 return 0; in ptp_ocp_ts_enable()
1987 iowrite32(0, ®->intr_mask); in ptp_ocp_ts_enable()
1988 iowrite32(0, ®->enable); in ptp_ocp_ts_enable()
1991 return 0; in ptp_ocp_ts_enable()
1997 ext->info->enable(ext, ~0, false); in ptp_ocp_unregister_ext()
2032 return 0; in ptp_ocp_register_ext()
2048 memset(&uart, 0, sizeof(uart)); in ptp_ocp_serial_line()
2052 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_serial_line()
2068 if (port.line < 0) in ptp_ocp_register_serial()
2076 return 0; in ptp_ocp_register_serial()
2090 return 0; in ptp_ocp_register_mem()
2099 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ in ptp_ocp_nmea_out_init()
2109 iowrite32(0, ®->enable); /* disable */ in _ptp_ocp_signal_init()
2121 for (i = 0; i < 4; i++) in ptp_ocp_signal_init()
2141 count = 0; in ptp_ocp_attr_group_add()
2142 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2151 count = 0; in ptp_ocp_attr_group_add()
2152 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2158 bp->attr_group[0] = NULL; in ptp_ocp_attr_group_add()
2173 ctrl |= enable ? bit : 0; in ptp_ocp_enable_fpga()
2209 ptp_ocp_irig_out(bp, val & 0x00100010); in __handle_signal_outputs()
2210 ptp_ocp_dcf_out(bp, val & 0x00200020); in __handle_signal_outputs()
2216 ptp_ocp_irig_in(bp, val & 0x00100010); in __handle_signal_inputs()
2217 ptp_ocp_dcf_in(bp, val & 0x00200020); in __handle_signal_inputs()
2233 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_get()
2235 return (ioread32(gpio) >> shift) & 0xffff; in ptp_ocp_sma_fb_get()
2246 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_output()
2248 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_output()
2261 return 0; in ptp_ocp_sma_fb_set_output()
2272 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_inputs()
2274 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_inputs()
2287 return 0; in ptp_ocp_sma_fb_set_inputs()
2297 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_sma_fb_init()
2301 for (i = 0; i < 4; i++) in ptp_ocp_sma_fb_init()
2306 for (i = 0; i < 4; i++) { in ptp_ocp_sma_fb_init()
2317 if (reg == 0xffffffff) { in ptp_ocp_sma_fb_init()
2318 for (i = 0; i < 4; i++) in ptp_ocp_sma_fb_init()
2322 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; in ptp_ocp_sma_fb_init()
2349 for (i = 0; i < 4; i++) { in ptp_ocp_fb_set_pins()
2357 return 0; in ptp_ocp_fb_set_pins()
2369 if ((version & 0xffff) == 0) { in ptp_ocp_fb_set_version()
2375 bp->fw_version = version & 0x7fff; in ptp_ocp_fb_set_version()
2436 int err = 0; in ptp_ocp_register_resources()
2460 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_art_sma_init()
2465 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ in ptp_ocp_art_sma_init()
2466 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ in ptp_ocp_art_sma_init()
2467 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ in ptp_ocp_art_sma_init()
2468 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ in ptp_ocp_art_sma_init()
2472 for (i = 0; i < 4; i++) { in ptp_ocp_art_sma_init()
2479 for (i = 0; i < 4; i++) { in ptp_ocp_art_sma_init()
2482 switch (reg & 0xff) { in ptp_ocp_art_sma_init()
2483 case 0: in ptp_ocp_art_sma_init()
2504 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; in ptp_ocp_art_sma_get()
2507 /* note: store 0 is considered invalid. */
2513 int err = 0; in ptp_ocp_art_sma_set()
2524 if (((reg >> 16) & val) == 0) { in ptp_ocp_art_sma_set()
2527 reg = (reg & 0xff00) | (val & 0xff); in ptp_ocp_art_sma_set()
2549 bp->flash_start = 0x1000000; in ptp_ocp_art_board_init()
2592 for (i = 0; tbl[i].name; i++) { in ptp_ocp_show_inputs()
2598 if (!val && def_val >= 0) { in ptp_ocp_show_inputs()
2624 idx = 0; in sma_parse_inputs()
2625 dir = *mode == SMA_MODE_IN ? 0 : 1; in sma_parse_inputs()
2626 if (!strcasecmp("IN:", argv[0])) { in sma_parse_inputs()
2627 dir = 0; in sma_parse_inputs()
2630 if (!strcasecmp("OUT:", argv[0])) { in sma_parse_inputs()
2634 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; in sma_parse_inputs()
2636 ret = 0; in sma_parse_inputs()
2639 if (ret < 0) in sma_parse_inputs()
2661 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); in ptp_ocp_sma_show()
2672 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); in sma1_show()
2688 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); in sma3_show()
2708 if (val < 0) in ptp_ocp_sma_store()
2717 return 0; in ptp_ocp_sma_store()
2724 ptp_ocp_sma_set_output(bp, sma_nr, 0); in ptp_ocp_sma_store()
2726 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); in ptp_ocp_sma_store()
2734 val = 0; in ptp_ocp_sma_store()
2798 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); in available_sma_inputs_show()
2851 err = kstrtou64(argv[argc], 0, &s.phase); in signal_store()
2857 err = kstrtoint(argv[argc], 0, &s.duty); in signal_store()
2863 err = kstrtou64(argv[argc], 0, &s.period); in signal_store()
2875 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); in signal_store()
2903 static EXT_ATTR_RW(signal, signal, 0);
2917 static EXT_ATTR_RO(signal, duty, 0);
2931 static EXT_ATTR_RO(signal, period, 0);
2945 static EXT_ATTR_RO(signal, phase, 0);
2960 static EXT_ATTR_RO(signal, polarity, 0);
2974 static EXT_ATTR_RO(signal, running, 0);
2990 static EXT_ATTR_RO(signal, start, 0);
3005 err = kstrtou32(buf, 0, &val); in seconds_store()
3008 if (val > 0xff) in seconds_store()
3012 val = (val << 8) | 0x1; in seconds_store()
3029 val = (val >> 8) & 0xff; in seconds_show()
3031 val = 0; in seconds_show()
3035 static EXT_ATTR_RW(freq, seconds, 0);
3055 return 0; in frequency_show()
3057 static EXT_ATTR_RO(freq, frequency, 0);
3107 err = kstrtou32(buf, 0, &val); in utc_tai_offset_store()
3135 err = kstrtou32(buf, 0, &val); in ts_window_adjust_store()
3152 val = (val >> 16) & 0x07; in irig_b_mode_show()
3167 err = kstrtou8(buf, 0, &val); in irig_b_mode_store()
3173 reg = ((val & 0x7) << 16); in irig_b_mode_store()
3176 iowrite32(0, &bp->irig_out->ctrl); /* disable */ in irig_b_mode_store()
3207 if (val < 0) in clock_source_store()
3277 u32 val = 0; in tod_correction_store()
3279 err = kstrtos32(buf, 0, &res); in tod_correction_store()
3282 if (res < 0) { in tod_correction_store()
3316 DEVICE_SIGNAL_GROUP(gen1, 0);
3336 DEVICE_FREQ_GROUP(freq1, 0);
3356 err = 0; in disciplining_config_read()
3393 err = nvmem_device_write(nvmem, 0x00, count, buf); in disciplining_config_write()
3418 err = 0; in temperature_table_read()
3426 err = nvmem_device_read(nvmem, 0x90 + off, count, buf); in temperature_table_read()
3455 err = nvmem_device_write(nvmem, 0x90, count, buf); in temperature_table_write()
3539 for (i = 0; i < 4; i++) { in gpio_input_map()
3542 if (map[i][0] & (1 << bit)) { in gpio_input_map()
3559 for (i = 0; i < 4; i++) { in gpio_output_map()
3608 val = (val >> 8) & 0xff; in _frequency_summary_show()
3656 memset(sma_val, 0xff, sizeof(sma_val)); in ptp_ocp_summary_show()
3661 sma_val[0][0] = reg & 0xffff; in ptp_ocp_summary_show()
3662 sma_val[1][0] = reg >> 16; in ptp_ocp_summary_show()
3665 sma_val[2][1] = reg & 0xffff; in ptp_ocp_summary_show()
3669 sma_val[2][0] = reg & 0xffff; in ptp_ocp_summary_show()
3670 sma_val[3][0] = reg >> 16; in ptp_ocp_summary_show()
3673 sma_val[0][1] = reg & 0xffff; in ptp_ocp_summary_show()
3679 sma_val[0][0], sma_val[0][1], buf); in ptp_ocp_summary_show()
3683 sma_val[1][0], sma_val[1][1], buf); in ptp_ocp_summary_show()
3687 sma_val[2][0], sma_val[2][1], buf); in ptp_ocp_summary_show()
3691 sma_val[3][0], sma_val[3][1], buf); in ptp_ocp_summary_show()
3747 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
3751 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
3799 if (val & 0x01) { in ptp_ocp_summary_show()
3800 gpio_input_map(src, bp, sma_val, 0, NULL); in ptp_ocp_summary_show()
3802 } else if (val & 0x02) { in ptp_ocp_summary_show()
3804 } else if (val & 0x04) { in ptp_ocp_summary_show()
3822 case 0: in ptp_ocp_summary_show()
3863 return 0; in ptp_ocp_summary_show()
3880 return 0; in ptp_ocp_tod_status_show()
3882 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); in ptp_ocp_tod_status_show()
3884 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; in ptp_ocp_tod_status_show()
3893 val >> 24, (val >> 16) & 0xff, val & 0xffff); in ptp_ocp_tod_status_show()
3896 seq_printf(s, "Status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
3904 seq_printf(s, "UTC status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
3906 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); in ptp_ocp_tod_status_show()
3908 val & TOD_STATUS_LEAP_VALID ? 1 : 0, in ptp_ocp_tod_status_show()
3909 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); in ptp_ocp_tod_status_show()
3914 return 0; in ptp_ocp_tod_status_show()
3968 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); in ptp_ocp_device_init()
3970 if (err < 0) { in ptp_ocp_device_init()
3999 return 0; in ptp_ocp_device_init()
4063 return 0; in ptp_ocp_complete()
4076 version >> 24, (version >> 16) & 0xff, version & 0xffff, in ptp_ocp_phc_info()
4158 for (i = 0; i < 4; i++) in ptp_ocp_detach()
4211 if (err < 0) { in ptp_ocp_probe()
4236 return 0; in ptp_ocp_probe()
4281 return 0; in ptp_ocp_i2c_notifier_call()
4285 return 0; in ptp_ocp_i2c_notifier_call()
4291 return 0; in ptp_ocp_i2c_notifier_call()
4300 return 0; in ptp_ocp_i2c_notifier_call()
4330 return 0; in ptp_ocp_init()