Lines Matching +full:soc +full:- +full:vdec
1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <soc/rockchip/pm_domains.h>
21 #include <dt-bindings/power/px30-power.h>
22 #include <dt-bindings/power/rockchip,rv1126-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3066-power.h>
25 #include <dt-bindings/power/rk3128-power.h>
26 #include <dt-bindings/power/rk3188-power.h>
27 #include <dt-bindings/power/rk3228-power.h>
28 #include <dt-bindings/power/rk3288-power.h>
29 #include <dt-bindings/power/rk3328-power.h>
30 #include <dt-bindings/power/rk3366-power.h>
31 #include <dt-bindings/power/rk3368-power.h>
32 #include <dt-bindings/power/rk3399-power.h>
33 #include <dt-bindings/power/rk3568-power.h>
34 #include <dt-bindings/power/rk3588-power.h>
177 * Dynamic Memory Controller may need to coordinate with us -- see
180 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
211 mutex_lock(&pmu->mutex); in rockchip_pmu_block()
215 * enabled for the duration of power-domain transitions. Most in rockchip_pmu_block()
217 * particular, DRAM DVFS / memory-controller idle) must be handled by in rockchip_pmu_block()
223 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_block()
224 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
227 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pmu_block()
229 dev_err(pmu->dev, in rockchip_pmu_block()
231 genpd->name, ret); in rockchip_pmu_block()
240 for (i = i - 1; i >= 0; i--) { in rockchip_pmu_block()
241 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
244 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_block()
247 mutex_unlock(&pmu->mutex); in rockchip_pmu_block()
264 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_unblock()
265 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_unblock()
268 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_unblock()
272 mutex_unlock(&pmu->mutex); in rockchip_pmu_unblock()
284 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
285 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
288 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
289 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
296 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
303 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
304 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
305 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
306 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
312 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
314 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
315 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
316 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
317 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
319 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
320 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
325 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
327 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
330 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
332 genpd->name, val); in rockchip_pmu_set_idle_request()
339 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
341 genpd->name, is_idle); in rockchip_pmu_set_idle_request()
352 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
353 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
355 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
356 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
358 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
359 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
361 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
362 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
364 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
365 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
367 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
376 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
377 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
379 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
380 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
382 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
383 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
385 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
386 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
388 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
389 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
391 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
399 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
402 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
403 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
405 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
408 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
409 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
412 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
415 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
420 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
423 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
424 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
427 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
432 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
435 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
436 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
439 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
444 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
445 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
452 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
454 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
460 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
461 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
467 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
469 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
473 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
474 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
480 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
482 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
492 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
493 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
494 u32 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
497 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
500 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
503 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
504 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
505 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
506 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
508 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
509 pd->info->pwr_mask, on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
518 dev_err(pmu->dev, in rockchip_do_pmu_set_power_domain()
520 genpd->name, is_on); in rockchip_do_pmu_set_power_domain()
527 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
530 mutex_lock(&pmu->mutex); in rockchip_pd_power()
533 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
535 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
536 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
556 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
559 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
584 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
593 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
610 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
627 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
630 return -EINVAL; in rockchip_pm_add_one_domain()
633 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
634 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
636 return -EINVAL; in rockchip_pm_add_one_domain()
639 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
642 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
644 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
646 return -EINVAL; in rockchip_pm_add_one_domain()
649 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
651 return -ENOMEM; in rockchip_pm_add_one_domain()
653 pd->info = pd_info; in rockchip_pm_add_one_domain()
654 pd->pmu = pmu; in rockchip_pm_add_one_domain()
656 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
657 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
658 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
659 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
660 if (!pd->clks) in rockchip_pm_add_one_domain()
661 return -ENOMEM; in rockchip_pm_add_one_domain()
663 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
664 node, pd->num_clks); in rockchip_pm_add_one_domain()
665 pd->num_clks = 0; in rockchip_pm_add_one_domain()
668 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
669 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
670 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
671 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
672 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
679 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
683 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", in rockchip_pm_add_one_domain()
686 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
687 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
688 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
690 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
691 error = -ENOMEM; in rockchip_pm_add_one_domain()
696 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, in rockchip_pm_add_one_domain()
697 pd->num_qos, in rockchip_pm_add_one_domain()
700 if (!pd->qos_save_regs[j]) { in rockchip_pm_add_one_domain()
701 error = -ENOMEM; in rockchip_pm_add_one_domain()
706 for (j = 0; j < pd->num_qos; j++) { in rockchip_pm_add_one_domain()
709 error = -ENODEV; in rockchip_pm_add_one_domain()
712 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); in rockchip_pm_add_one_domain()
713 if (IS_ERR(pd->qos_regmap[j])) { in rockchip_pm_add_one_domain()
714 error = -ENODEV; in rockchip_pm_add_one_domain()
722 if (pd->info->name) in rockchip_pm_add_one_domain()
723 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
725 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
726 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
727 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
728 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
729 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
730 pd->genpd.flags = GENPD_FLAG_PM_CLK; in rockchip_pm_add_one_domain()
731 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
732 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
733 pm_genpd_init(&pd->genpd, NULL, in rockchip_pm_add_one_domain()
735 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); in rockchip_pm_add_one_domain()
737 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
741 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
743 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
755 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
757 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
758 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
760 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
761 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
763 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
764 mutex_lock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
765 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
766 mutex_unlock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
777 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
778 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
793 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
795 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
810 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
815 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
819 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
826 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
831 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
835 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
836 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
839 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
840 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
855 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
856 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
866 return -ENODEV; in rockchip_pm_domain_probe()
869 match = of_match_device(dev->driver->of_match_table, dev); in rockchip_pm_domain_probe()
870 if (!match || !match->data) { in rockchip_pm_domain_probe()
872 return -EINVAL; in rockchip_pm_domain_probe()
875 pmu_info = match->data; in rockchip_pm_domain_probe()
878 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
881 return -ENOMEM; in rockchip_pm_domain_probe()
883 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
884 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
886 pmu->info = pmu_info; in rockchip_pm_domain_probe()
888 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
889 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
891 parent = dev->parent; in rockchip_pm_domain_probe()
894 return -ENODEV; in rockchip_pm_domain_probe()
897 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
898 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
900 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
907 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
908 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
909 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
910 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
911 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
912 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
914 error = -ENODEV; in rockchip_pm_domain_probe()
945 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
1029 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1058 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1109 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1320 .compatible = "rockchip,px30-power-controller",
1324 .compatible = "rockchip,rk3036-power-controller",
1328 .compatible = "rockchip,rk3066-power-controller",
1332 .compatible = "rockchip,rk3128-power-controller",
1336 .compatible = "rockchip,rk3188-power-controller",
1340 .compatible = "rockchip,rk3228-power-controller",
1344 .compatible = "rockchip,rk3288-power-controller",
1348 .compatible = "rockchip,rk3328-power-controller",
1352 .compatible = "rockchip,rk3366-power-controller",
1356 .compatible = "rockchip,rk3368-power-controller",
1360 .compatible = "rockchip,rk3399-power-controller",
1364 .compatible = "rockchip,rk3568-power-controller",
1368 .compatible = "rockchip,rk3588-power-controller",
1372 .compatible = "rockchip,rv1126-power-controller",
1381 .name = "rockchip-pm-domain",