Lines Matching refs:drv
251 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
253 return !drv->loop_disabled; in cpr_is_allowed()
256 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
258 writel_relaxed(value, drv->base + offset); in cpr_write()
261 static u32 cpr_read(struct cpr_drv *drv, u32 offset) in cpr_read() argument
263 return readl_relaxed(drv->base + offset); in cpr_read()
267 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value) in cpr_masked_write() argument
271 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
274 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
277 static void cpr_irq_clr(struct cpr_drv *drv) in cpr_irq_clr() argument
279 cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL); in cpr_irq_clr()
282 static void cpr_irq_clr_nack(struct cpr_drv *drv) in cpr_irq_clr_nack() argument
284 cpr_irq_clr(drv); in cpr_irq_clr_nack()
285 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_irq_clr_nack()
288 static void cpr_irq_clr_ack(struct cpr_drv *drv) in cpr_irq_clr_ack() argument
290 cpr_irq_clr(drv); in cpr_irq_clr_ack()
291 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_irq_clr_ack()
294 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits) in cpr_irq_set() argument
296 cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits); in cpr_irq_set()
299 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value) in cpr_ctl_modify() argument
301 cpr_masked_write(drv, REG_RBCPR_CTL, mask, value); in cpr_ctl_modify()
304 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner) in cpr_ctl_enable() argument
307 const struct cpr_desc *desc = drv->desc; in cpr_ctl_enable()
313 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); in cpr_ctl_enable()
314 cpr_masked_write(drv, REG_RBCPR_CTL, in cpr_ctl_enable()
318 cpr_irq_set(drv, corner->save_irq); in cpr_ctl_enable()
320 if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV) in cpr_ctl_enable()
324 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val); in cpr_ctl_enable()
327 static void cpr_ctl_disable(struct cpr_drv *drv) in cpr_ctl_disable() argument
329 cpr_irq_set(drv, 0); in cpr_ctl_disable()
330 cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN | in cpr_ctl_disable()
332 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, in cpr_ctl_disable()
335 cpr_irq_clr(drv); in cpr_ctl_disable()
336 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_ctl_disable()
337 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_ctl_disable()
338 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0); in cpr_ctl_disable()
341 static bool cpr_ctl_is_enabled(struct cpr_drv *drv) in cpr_ctl_is_enabled() argument
345 reg_val = cpr_read(drv, REG_RBCPR_CTL); in cpr_ctl_is_enabled()
349 static bool cpr_ctl_is_busy(struct cpr_drv *drv) in cpr_ctl_is_busy() argument
353 reg_val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_ctl_is_busy()
357 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner) in cpr_corner_save() argument
359 corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_corner_save()
360 corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0)); in cpr_corner_save()
363 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner) in cpr_corner_restore() argument
367 const struct cpr_desc *desc = drv->desc; in cpr_corner_restore()
371 gcnt = drv->gcnt; in cpr_corner_restore()
377 cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot); in cpr_corner_restore()
381 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_corner_restore()
383 cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt); in cpr_corner_restore()
385 cpr_write(drv, REG_RBCPR_CTL, ctl); in cpr_corner_restore()
387 cpr_irq_set(drv, irq); in cpr_corner_restore()
388 dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt, in cpr_corner_restore()
407 static int cpr_pre_voltage(struct cpr_drv *drv, in cpr_pre_voltage() argument
411 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_pre_voltage()
413 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
414 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
419 static int cpr_post_voltage(struct cpr_drv *drv, in cpr_post_voltage() argument
423 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_post_voltage()
425 if (drv->tcsr && dir == UP) in cpr_post_voltage()
426 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
431 static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner, in cpr_scale_voltage() argument
437 ret = cpr_pre_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
441 ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV); in cpr_scale_voltage()
443 dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n", in cpr_scale_voltage()
448 ret = cpr_post_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
455 static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv) in cpr_get_cur_perf_state() argument
457 return drv->corner ? drv->corner - drv->corners + 1 : 0; in cpr_get_cur_perf_state()
460 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir) in cpr_scale() argument
465 const struct cpr_desc *desc = drv->desc; in cpr_scale()
470 step_uV = regulator_get_linear_step(drv->vdd_apc); in cpr_scale()
474 corner = drv->corner; in cpr_scale()
476 val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_scale()
495 cpr_irq_clr_nack(drv); in cpr_scale()
501 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
504 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP); in cpr_scale()
516 dev_dbg(drv->dev, in cpr_scale()
518 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
532 cpr_irq_clr_nack(drv); in cpr_scale()
538 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
541 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN); in cpr_scale()
553 dev_dbg(drv->dev, in cpr_scale()
555 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
558 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_scale()
560 cpr_irq_clr_nack(drv); in cpr_scale()
563 drv->corner->last_uV = new_uV; in cpr_scale()
577 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
580 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_scale()
583 cpr_irq_clr_ack(drv); in cpr_scale()
590 struct cpr_drv *drv = dev; in cpr_irq_handler() local
591 const struct cpr_desc *desc = drv->desc; in cpr_irq_handler()
595 mutex_lock(&drv->lock); in cpr_irq_handler()
597 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
598 if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS) in cpr_irq_handler()
599 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
601 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val); in cpr_irq_handler()
603 if (!cpr_ctl_is_enabled(drv)) { in cpr_irq_handler()
604 dev_dbg(drv->dev, "CPR is disabled\n"); in cpr_irq_handler()
606 } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) { in cpr_irq_handler()
607 dev_dbg(drv->dev, "CPR measurement is not ready\n"); in cpr_irq_handler()
608 } else if (!cpr_is_allowed(drv)) { in cpr_irq_handler()
609 val = cpr_read(drv, REG_RBCPR_CTL); in cpr_irq_handler()
610 dev_err_ratelimited(drv->dev, in cpr_irq_handler()
620 cpr_scale(drv, UP); in cpr_irq_handler()
622 cpr_scale(drv, DOWN); in cpr_irq_handler()
624 cpr_irq_clr_nack(drv); in cpr_irq_handler()
626 cpr_irq_clr_nack(drv); in cpr_irq_handler()
629 dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n"); in cpr_irq_handler()
631 dev_dbg(drv->dev, in cpr_irq_handler()
636 cpr_corner_save(drv, drv->corner); in cpr_irq_handler()
639 mutex_unlock(&drv->lock); in cpr_irq_handler()
644 static int cpr_enable(struct cpr_drv *drv) in cpr_enable() argument
648 ret = regulator_enable(drv->vdd_apc); in cpr_enable()
652 mutex_lock(&drv->lock); in cpr_enable()
654 if (cpr_is_allowed(drv) && drv->corner) { in cpr_enable()
655 cpr_irq_clr(drv); in cpr_enable()
656 cpr_corner_restore(drv, drv->corner); in cpr_enable()
657 cpr_ctl_enable(drv, drv->corner); in cpr_enable()
660 mutex_unlock(&drv->lock); in cpr_enable()
665 static int cpr_disable(struct cpr_drv *drv) in cpr_disable() argument
667 mutex_lock(&drv->lock); in cpr_disable()
669 if (cpr_is_allowed(drv)) { in cpr_disable()
670 cpr_ctl_disable(drv); in cpr_disable()
671 cpr_irq_clr(drv); in cpr_disable()
674 mutex_unlock(&drv->lock); in cpr_disable()
676 return regulator_disable(drv->vdd_apc); in cpr_disable()
679 static int cpr_config(struct cpr_drv *drv) in cpr_config() argument
684 const struct cpr_desc *desc = drv->desc; in cpr_config()
687 cpr_write(drv, REG_RBIF_IRQ_EN(0), 0); in cpr_config()
688 cpr_write(drv, REG_RBCPR_CTL, 0); in cpr_config()
694 cpr_write(drv, REG_RBIF_LIMIT, val); in cpr_config()
695 cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT); in cpr_config()
702 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_config()
705 gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000; in cpr_config()
708 drv->gcnt = gcnt; in cpr_config()
711 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000; in cpr_config()
712 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val); in cpr_config()
713 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val, in cpr_config()
720 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val); in cpr_config()
727 cpr_write(drv, REG_RBCPR_CTL, val); in cpr_config()
729 for (i = 0; i < drv->num_corners; i++) { in cpr_config()
730 corner = &drv->corners[i]; in cpr_config()
735 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_config()
737 val = cpr_read(drv, REG_RBCPR_VERSION); in cpr_config()
739 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS; in cpr_config()
747 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_set_performance_state() local
752 mutex_lock(&drv->lock); in cpr_set_performance_state()
754 dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n", in cpr_set_performance_state()
755 __func__, state, cpr_get_cur_perf_state(drv)); in cpr_set_performance_state()
761 corner = drv->corners + state - 1; in cpr_set_performance_state()
762 end = &drv->corners[drv->num_corners - 1]; in cpr_set_performance_state()
763 if (corner > end || corner < drv->corners) { in cpr_set_performance_state()
769 if (drv->corner > corner) in cpr_set_performance_state()
771 else if (drv->corner < corner) in cpr_set_performance_state()
776 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
781 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
782 cpr_ctl_disable(drv); in cpr_set_performance_state()
784 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_set_performance_state()
788 if (cpr_is_allowed(drv)) { in cpr_set_performance_state()
789 cpr_irq_clr(drv); in cpr_set_performance_state()
790 if (drv->corner != corner) in cpr_set_performance_state()
791 cpr_corner_restore(drv, corner); in cpr_set_performance_state()
792 cpr_ctl_enable(drv, corner); in cpr_set_performance_state()
795 drv->corner = corner; in cpr_set_performance_state()
798 mutex_unlock(&drv->lock); in cpr_set_performance_state()
804 cpr_populate_ring_osc_idx(struct cpr_drv *drv) in cpr_populate_ring_osc_idx() argument
806 struct fuse_corner *fuse = drv->fuse_corners; in cpr_populate_ring_osc_idx()
807 struct fuse_corner *end = fuse + drv->desc->num_fuse_corners; in cpr_populate_ring_osc_idx()
808 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx()
813 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); in cpr_populate_ring_osc_idx()
826 struct cpr_drv *drv) in cpr_read_fuse_uV() argument
832 ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); in cpr_read_fuse_uV()
847 static int cpr_fuse_corner_init(struct cpr_drv *drv) in cpr_fuse_corner_init() argument
849 const struct cpr_desc *desc = drv->desc; in cpr_fuse_corner_init()
850 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init()
851 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_fuse_corner_init()
862 step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_fuse_corner_init()
867 fuse = drv->fuse_corners; in cpr_fuse_corner_init()
882 step_volt, drv); in cpr_fuse_corner_init()
901 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); in cpr_fuse_corner_init()
920 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) { in cpr_fuse_corner_init()
926 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
930 dev_err(drv->dev, in cpr_fuse_corner_init()
936 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
940 dev_err(drv->dev, in cpr_fuse_corner_init()
946 dev_dbg(drv->dev, in cpr_fuse_corner_init()
956 struct cpr_drv *drv, in cpr_calculate_scaling() argument
970 ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); in cpr_calculate_scaling()
1075 static int cpr_corner_init(struct cpr_drv *drv) in cpr_corner_init() argument
1077 const struct cpr_desc *desc = drv->desc; in cpr_corner_init()
1078 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_corner_init()
1089 int step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_corner_init()
1095 corner = drv->corners; in cpr_corner_init()
1096 end = &corner[drv->num_corners - 1]; in cpr_corner_init()
1098 cdata = devm_kcalloc(drv->dev, drv->num_corners, in cpr_corner_init()
1108 for (level = 1; level <= drv->num_corners; level++) { in cpr_corner_init()
1109 opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level); in cpr_corner_init()
1118 freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev); in cpr_corner_init()
1126 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1127 dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n", in cpr_corner_init()
1177 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1179 prev_fuse = &drv->fuse_corners[fnum - 1]; in cpr_corner_init()
1188 scaling = cpr_calculate_scaling(quot_offset, drv, in cpr_corner_init()
1218 dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i, in cpr_corner_init()
1226 static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv) in cpr_get_fuses() argument
1228 const struct cpr_desc *desc = drv->desc; in cpr_get_fuses()
1232 fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners, in cpr_get_fuses()
1242 fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1247 fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1253 fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1258 fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1267 static void cpr_set_loop_allowed(struct cpr_drv *drv) in cpr_set_loop_allowed() argument
1269 drv->loop_disabled = false; in cpr_set_loop_allowed()
1272 static int cpr_init_parameters(struct cpr_drv *drv) in cpr_init_parameters() argument
1274 const struct cpr_desc *desc = drv->desc; in cpr_init_parameters()
1277 clk = clk_get(drv->dev, "ref"); in cpr_init_parameters()
1281 drv->ref_clk_khz = clk_get_rate(clk) / 1000; in cpr_init_parameters()
1292 dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n", in cpr_init_parameters()
1298 static int cpr_find_initial_corner(struct cpr_drv *drv) in cpr_find_initial_corner() argument
1305 if (!drv->cpu_clk) { in cpr_find_initial_corner()
1306 dev_err(drv->dev, "cannot get rate from NULL clk\n"); in cpr_find_initial_corner()
1310 end = &drv->corners[drv->num_corners - 1]; in cpr_find_initial_corner()
1311 rate = clk_get_rate(drv->cpu_clk); in cpr_find_initial_corner()
1324 for (iter = drv->corners; iter <= end; iter++) { in cpr_find_initial_corner()
1329 drv->corner = iter; in cpr_find_initial_corner()
1333 drv->corner = iter; in cpr_find_initial_corner()
1336 if (!drv->corner) { in cpr_find_initial_corner()
1337 dev_err(drv->dev, "boot up corner not found\n"); in cpr_find_initial_corner()
1341 dev_dbg(drv->dev, "boot up perf state: %u\n", i); in cpr_find_initial_corner()
1435 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_off() local
1437 return cpr_disable(drv); in cpr_power_off()
1442 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_on() local
1444 return cpr_enable(drv); in cpr_power_on()
1450 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_pd_attach_dev() local
1451 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_pd_attach_dev()
1454 mutex_lock(&drv->lock); in cpr_pd_attach_dev()
1456 dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev)); in cpr_pd_attach_dev()
1465 if (drv->attached_cpu_dev) in cpr_pd_attach_dev()
1477 drv->cpu_clk = devm_clk_get(dev, NULL); in cpr_pd_attach_dev()
1478 if (IS_ERR(drv->cpu_clk)) { in cpr_pd_attach_dev()
1479 ret = PTR_ERR(drv->cpu_clk); in cpr_pd_attach_dev()
1481 dev_err(drv->dev, "could not get cpu clk: %d\n", ret); in cpr_pd_attach_dev()
1484 drv->attached_cpu_dev = dev; in cpr_pd_attach_dev()
1486 dev_dbg(drv->dev, "using cpu clk from: %s\n", in cpr_pd_attach_dev()
1487 dev_name(drv->attached_cpu_dev)); in cpr_pd_attach_dev()
1497 ret = dev_pm_opp_get_opp_count(&drv->pd.dev); in cpr_pd_attach_dev()
1499 dev_err(drv->dev, "could not get OPP count\n"); in cpr_pd_attach_dev()
1502 drv->num_corners = ret; in cpr_pd_attach_dev()
1504 if (drv->num_corners < 2) { in cpr_pd_attach_dev()
1505 dev_err(drv->dev, "need at least 2 OPPs to use CPR\n"); in cpr_pd_attach_dev()
1510 drv->corners = devm_kcalloc(drv->dev, drv->num_corners, in cpr_pd_attach_dev()
1511 sizeof(*drv->corners), in cpr_pd_attach_dev()
1513 if (!drv->corners) { in cpr_pd_attach_dev()
1518 ret = cpr_corner_init(drv); in cpr_pd_attach_dev()
1522 cpr_set_loop_allowed(drv); in cpr_pd_attach_dev()
1524 ret = cpr_init_parameters(drv); in cpr_pd_attach_dev()
1529 ret = cpr_config(drv); in cpr_pd_attach_dev()
1533 ret = cpr_find_initial_corner(drv); in cpr_pd_attach_dev()
1538 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1543 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
1547 dev_info(drv->dev, "driver initialized with %u OPPs\n", in cpr_pd_attach_dev()
1548 drv->num_corners); in cpr_pd_attach_dev()
1551 mutex_unlock(&drv->lock); in cpr_pd_attach_dev()
1560 struct cpr_drv *drv = s->private; in cpr_debug_info_show() local
1564 corner = drv->corner; in cpr_debug_info_show()
1571 gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel)); in cpr_debug_info_show()
1574 ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_debug_info_show()
1577 irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_debug_info_show()
1580 reg = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_debug_info_show()
1606 static void cpr_debugfs_init(struct cpr_drv *drv) in cpr_debugfs_init() argument
1608 drv->debugfs = debugfs_create_dir("qcom_cpr", NULL); in cpr_debugfs_init()
1610 debugfs_create_file("debug_info", 0444, drv->debugfs, in cpr_debugfs_init()
1611 drv, &cpr_debug_info_fops); in cpr_debugfs_init()
1617 struct cpr_drv *drv; in cpr_probe() local
1627 drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); in cpr_probe()
1628 if (!drv) in cpr_probe()
1630 drv->dev = dev; in cpr_probe()
1631 drv->desc = data->cpr_desc; in cpr_probe()
1632 drv->acc_desc = data->acc_desc; in cpr_probe()
1634 drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners, in cpr_probe()
1635 sizeof(*drv->fuse_corners), in cpr_probe()
1637 if (!drv->fuse_corners) in cpr_probe()
1644 drv->tcsr = syscon_node_to_regmap(np); in cpr_probe()
1646 if (IS_ERR(drv->tcsr)) in cpr_probe()
1647 return PTR_ERR(drv->tcsr); in cpr_probe()
1649 drv->base = devm_platform_ioremap_resource(pdev, 0); in cpr_probe()
1650 if (IS_ERR(drv->base)) in cpr_probe()
1651 return PTR_ERR(drv->base); in cpr_probe()
1657 drv->vdd_apc = devm_regulator_get(dev, "vdd-apc"); in cpr_probe()
1658 if (IS_ERR(drv->vdd_apc)) in cpr_probe()
1659 return PTR_ERR(drv->vdd_apc); in cpr_probe()
1672 drv->cpr_fuses = cpr_get_fuses(drv); in cpr_probe()
1673 if (IS_ERR(drv->cpr_fuses)) in cpr_probe()
1674 return PTR_ERR(drv->cpr_fuses); in cpr_probe()
1676 ret = cpr_populate_ring_osc_idx(drv); in cpr_probe()
1680 ret = cpr_fuse_corner_init(drv); in cpr_probe()
1684 mutex_init(&drv->lock); in cpr_probe()
1689 "cpr", drv); in cpr_probe()
1693 drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name, in cpr_probe()
1695 if (!drv->pd.name) in cpr_probe()
1698 drv->pd.power_off = cpr_power_off; in cpr_probe()
1699 drv->pd.power_on = cpr_power_on; in cpr_probe()
1700 drv->pd.set_performance_state = cpr_set_performance_state; in cpr_probe()
1701 drv->pd.opp_to_performance_state = cpr_get_performance_state; in cpr_probe()
1702 drv->pd.attach_dev = cpr_pd_attach_dev; in cpr_probe()
1704 ret = pm_genpd_init(&drv->pd, NULL, true); in cpr_probe()
1708 ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd); in cpr_probe()
1712 platform_set_drvdata(pdev, drv); in cpr_probe()
1713 cpr_debugfs_init(drv); in cpr_probe()
1718 pm_genpd_remove(&drv->pd); in cpr_probe()
1724 struct cpr_drv *drv = platform_get_drvdata(pdev); in cpr_remove() local
1726 if (cpr_is_allowed(drv)) { in cpr_remove()
1727 cpr_ctl_disable(drv); in cpr_remove()
1728 cpr_irq_set(drv, 0); in cpr_remove()
1732 pm_genpd_remove(&drv->pd); in cpr_remove()
1734 debugfs_remove_recursive(drv->debugfs); in cpr_remove()