pinctrl/visconti/pinctrl-tmpv7700.c

22 #define REG_PINMUX3	0x3008  macro
166 	VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000),
167 	VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000),
178 	VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000),
185 	VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111),
186 	VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000),
190 	VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222),
191 	VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000),
197 	VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005),
198 	VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050),
199 	VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500),
200 	VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000),
201 	VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000),
202 	VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000),
203 	VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000),
204 	VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000),
289 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),
290 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),
291 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),
292 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)),
293 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)),
294 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)),
295 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)),
296 	tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)),