pinctrl/tegra/pinctrl-tegra124.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Pinctrl data for the NVIDIA Tegra124 pinmux
7  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
14 #include <linux/pinctrl/pinmux.h>
16 #include "pinctrl-tegra.h"
19  * Most pins affected by the pinmux can also be GPIOs. Define these first.
208 /* All non-GPIO pins follow */
212 /* Non-GPIO pins */
1709 #define DRV_PINGROUP_REG(r)		((r) - DRV_PINGROUP_REG_A)
1710 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
1711 #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r)	((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1714 #define PINGROUP_BIT_N(b)		(-1)
1741 		.drv_reg = -1,						\
1752 		.mux_reg = -1,						\
1753 		.pupd_reg = -1,						\
1754 		.tri_reg = -1,						\
1755 		.einput_bit = -1,					\
1756 		.odrain_bit = -1,					\
1757 		.lock_bit = -1,						\
1758 		.ioreset_bit = -1,					\
1759 		.rcv_sel_bit = -1,					\
1791 		.pupd_reg = -1,						\
1792 		.tri_reg = -1,						\
1793 		.einput_bit = -1,					\
1794 		.odrain_bit = -1,					\
1795 		.lock_bit = -1,						\
1796 		.ioreset_bit = -1,					\
1797 		.rcv_sel_bit = -1,					\
1798 		.drv_reg = -1,						\
2010 	DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2016 	DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2031 	DRV_PINGROUP(ao3,         0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2033 	DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2043 	.gpio_compatible = "nvidia,tegra124-gpio",
2061 	{ .compatible = "nvidia,tegra124-pinmux", },
2067 		.name = "tegra124-pinctrl",