Lines Matching +full:off +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
26 #include "../pinctrl-utils.h"
34 struct gpio_chip chip; member
38 static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_first_readl() argument
40 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_readl()
43 static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) in sppctl_first_writel() argument
45 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_writel()
48 static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_master_readl() argument
50 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_readl()
54 u32 off) in sppctl_gpio_master_writel() argument
56 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_writel()
59 static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_oe_readl() argument
61 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); in sppctl_gpio_oe_readl()
64 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) in sppctl_gpio_oe_writel() argument
66 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); in sppctl_gpio_oe_writel()
69 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) in sppctl_gpio_out_writel() argument
71 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); in sppctl_gpio_out_writel()
74 static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_in_readl() argument
76 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); in sppctl_gpio_in_readl()
79 static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_iinv_readl() argument
81 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); in sppctl_gpio_iinv_readl()
85 u32 off) in sppctl_gpio_iinv_writel() argument
87 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); in sppctl_gpio_iinv_writel()
90 static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_oinv_readl() argument
92 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); in sppctl_gpio_oinv_readl()
96 u32 off) in sppctl_gpio_oinv_writel() argument
98 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); in sppctl_gpio_oinv_writel()
101 static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) in sppctl_gpio_od_readl() argument
103 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); in sppctl_gpio_od_readl()
106 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) in sppctl_gpio_od_writel() argument
108 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); in sppctl_gpio_od_writel()
127 * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. in sppctl_get_moon_reg_and_bit_offset()
128 * The lower 16-bit word are the control-fields. The corresponding in sppctl_get_moon_reg_and_bit_offset()
129 * bits in mask-field should be set then you can write something to in sppctl_get_moon_reg_and_bit_offset()
130 * control-field. in sppctl_get_moon_reg_and_bit_offset()
150 * sppctl_func_set() - Set pin of fully-pinmux function.
152 * Mask-fields and control-fields of fully-pinmux function of SP7021 are
155 * func# | register | mask-field | control-field
156 * -------+----------+--------------+---------------
163 * where mask-fields are used to protect control-fields from write-in
164 * accidentally. Set the corresponding bits in the mask-field before
165 * you write a value into a control-field.
167 * Control-fields are used to set where the function pin is going to
170 * Note that mask-fields and control-fields of even number of 'func'
179 * Note that upper 16-bit word are mask-fields and lower 16-bit in sppctl_func_set()
180 * word are the control-fields. Set corresponding bits in mask- in sppctl_func_set()
181 * field before write to a control-field. in sppctl_func_set()
186 * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin in sppctl_func_set()
189 func -= MUXF_L2SW_CLK_OUT; in sppctl_func_set()
192 * Check if 'func' is an odd number or not. Mask and control- in sppctl_func_set()
203 writel(reg, pctl->moon2_base + offset); in sppctl_func_set()
207 * sppctl_gmx_set() - Set pin of group-pinmux.
209 * Mask-fields and control-fields of group-pinmux function of SP7021 are
212 * register | mask-fields | control-fields
213 * ----------+--------------+----------------
219 * where mask-fields are used to protect control-fields from write-in
220 * accidentally. Set the corresponding bits in the mask-field before
221 * you write a value into a control-field.
223 * Control-fields are used to set where the function pin is going to
224 * be routed to. A control-field consists of one or more bits.
232 * Note that upper 16-bit word are mask-fields and lower 16-bit in sppctl_gmx_set()
233 * word are the control-fields. Set corresponding bits in mask- in sppctl_gmx_set()
234 * field before write to a control-field. in sppctl_gmx_set()
236 mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; in sppctl_gmx_set()
239 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
243 * sppctl_first_get() - get bit of FIRST register.
245 * There are 4 FIRST registers. Each has 32 control-bits.
246 * Totally, there are 4 * 32 = 128 control-bits.
247 * Control-bits are arranged as shown below:
249 * registers | control-bits
250 * -----------+--------------
256 * Each control-bit sets type of a GPIO pin.
257 * 0: a fully-pinmux pin
260 static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) in sppctl_first_get() argument
262 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_first_get()
272 * sppctl_master_get() - get bit of MASTER register.
274 * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits.
275 * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are
276 * control-bits. Totally, there are 128 mask-bits and 128 control-bits.
279 * register | mask-bits | control-bits
280 * -----------+-------------+--------------
287 * where mask-bits are used to protect control-bits from write-in
288 * accidentally. Set the corresponding mask-bit before you write
289 * a value into a control-bit.
291 * Each control-bit sets type of a GPIO pin when FIRST bit is 1.
295 static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) in sppctl_master_get() argument
297 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_master_get()
305 static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, in sppctl_first_master_set() argument
308 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_first_master_set()
342 static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_input_inv_set() argument
344 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_input_inv_set()
351 static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_output_inv_set() argument
353 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_output_inv_set()
360 static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_output_od_get() argument
362 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_output_od_get()
371 static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, in sppctl_gpio_output_od_set() argument
374 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_output_od_set()
381 static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_get_direction() argument
383 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_get_direction()
392 static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_inv_get() argument
394 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_inv_get()
400 spin_lock_irqsave(&spp_gchip->lock, flags); in sppctl_gpio_inv_get()
402 if (sppctl_gpio_get_direction(chip, offset)) in sppctl_gpio_inv_get()
407 spin_unlock_irqrestore(&spp_gchip->lock, flags); in sppctl_gpio_inv_get()
412 static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_direction_input() argument
414 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_direction_input()
420 spin_lock_irqsave(&spp_gchip->lock, flags); in sppctl_gpio_direction_input()
424 spin_unlock_irqrestore(&spp_gchip->lock, flags); in sppctl_gpio_direction_input()
428 static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) in sppctl_gpio_direction_output() argument
430 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_direction_output()
436 spin_lock_irqsave(&spp_gchip->lock, flags); in sppctl_gpio_direction_output()
441 spin_unlock_irqrestore(&spp_gchip->lock, flags); in sppctl_gpio_direction_output()
448 spin_unlock_irqrestore(&spp_gchip->lock, flags); in sppctl_gpio_direction_output()
452 static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) in sppctl_gpio_get() argument
454 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_get()
463 static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) in sppctl_gpio_set() argument
465 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_set()
472 static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, in sppctl_gpio_set_config() argument
476 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); in sppctl_gpio_set_config()
489 return sppctl_gpio_direction_output(chip, offset, 0); in sppctl_gpio_set_config()
492 return -ENOTSUPP; in sppctl_gpio_set_config()
495 return -EINVAL; in sppctl_gpio_set_config()
501 static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) in sppctl_gpio_dbg_show() argument
506 for (i = 0; i < chip->ngpio; i++) { in sppctl_gpio_dbg_show()
507 label = gpiochip_is_requested(chip, i); in sppctl_gpio_dbg_show()
511 seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, in sppctl_gpio_dbg_show()
512 chip->names[i], label); in sppctl_gpio_dbg_show()
513 seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); in sppctl_gpio_dbg_show()
514 seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); in sppctl_gpio_dbg_show()
515 seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); in sppctl_gpio_dbg_show()
516 seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); in sppctl_gpio_dbg_show()
517 seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); in sppctl_gpio_dbg_show()
518 seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); in sppctl_gpio_dbg_show()
529 spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); in sppctl_gpio_new()
531 return -ENOMEM; in sppctl_gpio_new()
532 pctl->spp_gchip = spp_gchip; in sppctl_gpio_new()
534 spp_gchip->gpioxt_base = pctl->gpioxt_base; in sppctl_gpio_new()
535 spp_gchip->first_base = pctl->first_base; in sppctl_gpio_new()
536 spin_lock_init(&spp_gchip->lock); in sppctl_gpio_new()
538 gchip = &spp_gchip->chip; in sppctl_gpio_new()
539 gchip->label = SPPCTL_MODULE_NAME; in sppctl_gpio_new()
540 gchip->parent = &pdev->dev; in sppctl_gpio_new()
541 gchip->owner = THIS_MODULE; in sppctl_gpio_new()
542 gchip->request = gpiochip_generic_request; in sppctl_gpio_new()
543 gchip->free = gpiochip_generic_free; in sppctl_gpio_new()
544 gchip->get_direction = sppctl_gpio_get_direction; in sppctl_gpio_new()
545 gchip->direction_input = sppctl_gpio_direction_input; in sppctl_gpio_new()
546 gchip->direction_output = sppctl_gpio_direction_output; in sppctl_gpio_new()
547 gchip->get = sppctl_gpio_get; in sppctl_gpio_new()
548 gchip->set = sppctl_gpio_set; in sppctl_gpio_new()
549 gchip->set_config = sppctl_gpio_set_config; in sppctl_gpio_new()
550 gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ? in sppctl_gpio_new()
552 gchip->base = -1; in sppctl_gpio_new()
553 gchip->ngpio = sppctl_gpio_list_sz; in sppctl_gpio_new()
554 gchip->names = sppctl_gpio_list_s; in sppctl_gpio_new()
556 pctl->pctl_grange.npins = gchip->ngpio; in sppctl_gpio_new()
557 pctl->pctl_grange.name = gchip->label; in sppctl_gpio_new()
558 pctl->pctl_grange.gc = gchip; in sppctl_gpio_new()
560 err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); in sppctl_gpio_new()
562 return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); in sppctl_gpio_new()
576 if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) in sppctl_pin_config_get()
577 return -EINVAL; in sppctl_pin_config_get()
582 if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) in sppctl_pin_config_get()
583 return -EINVAL; in sppctl_pin_config_get()
584 if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) in sppctl_pin_config_get()
585 return -EINVAL; in sppctl_pin_config_get()
586 if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) in sppctl_pin_config_get()
587 return -EINVAL; in sppctl_pin_config_get()
588 arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); in sppctl_pin_config_get()
592 return -EOPNOTSUPP; in sppctl_pin_config_get()
607 sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); in sppctl_pin_config_set()
613 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); in sppctl_pin_config_set()
615 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); in sppctl_pin_config_set()
617 sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); in sppctl_pin_config_set()
619 sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); in sppctl_pin_config_set()
621 sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); in sppctl_pin_config_set()
652 switch (f->type) { in sppctl_get_function_groups()
659 if (!f->grps) in sppctl_get_function_groups()
662 *num_groups = f->gnum; in sppctl_get_function_groups()
663 for (i = 0; i < pctl->unq_grps_sz; i++) in sppctl_get_function_groups()
664 if (pctl->g2fp_maps[i].f_idx == selector) in sppctl_get_function_groups()
666 *groups = &pctl->unq_grps[i]; in sppctl_get_function_groups()
670 dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", in sppctl_get_function_groups()
671 selector, f->type); in sppctl_get_function_groups()
679 * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting
681 * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by
682 * settings its control-field. Refer to following table:
684 * control-field | GPIO
685 * --------------+--------
695 return (offset < 8) ? 0 : offset - 7; in sppctl_fully_pinmux_conv()
703 struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; in sppctl_set_mux()
706 switch (f->type) { in sppctl_set_mux()
708 sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, in sppctl_set_mux()
714 for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) in sppctl_set_mux()
715 sppctl_first_master_set(&pctl->spp_gchip->chip, in sppctl_set_mux()
716 f->grps[g2fpm.g_idx].pins[i], in sppctl_set_mux()
718 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); in sppctl_set_mux()
722 dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", in sppctl_set_mux()
723 func_selector, f->type); in sppctl_set_mux()
736 g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); in sppctl_gpio_request_enable()
737 g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); in sppctl_gpio_request_enable()
741 sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); in sppctl_gpio_request_enable()
758 return pctl->unq_grps_sz; in sppctl_get_groups_count()
765 return pctl->unq_grps[selector]; in sppctl_get_group_name()
772 struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; in sppctl_get_group_pins()
778 /* Except group-pinmux, each group has 1 pin. */ in sppctl_get_group_pins()
779 if (f->type != pinmux_type_grp) { in sppctl_get_group_pins()
785 /* Group-pinmux may have more than one pin. */ in sppctl_get_group_pins()
786 if (!f->grps) in sppctl_get_group_pins()
789 if (f->gnum < 1) in sppctl_get_group_pins()
792 *num_pins = f->grps[g2fpm.g_idx].pnum; in sppctl_get_group_pins()
793 *pins = f->grps[g2fpm.g_idx].pins; in sppctl_get_group_pins()
806 first = sppctl_first_get(&pctl->spp_gchip->chip, offset); in sppctl_pin_dbg_show()
807 master = sppctl_master_get(&pctl->spp_gchip->chip, offset); in sppctl_pin_dbg_show()
842 * Each 32-bit integer defines a individual pin in which: in sppctl_dt_node_to_map()
845 * Bit 23~16: defines types: (1) fully-pinmux pins in sppctl_dt_node_to_map()
849 * 'include/dt-binging/pinctrl/sppctl.h'). in sppctl_dt_node_to_map()
850 * Bit 7~0: defines types or initial-state of digital GPIO pins. in sppctl_dt_node_to_map()
857 dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", in sppctl_dt_node_to_map()
859 return -EINVAL; in sppctl_dt_node_to_map()
868 return -ENOMEM; in sppctl_dt_node_to_map()
876 (*map)[i].name = parent->name; in sppctl_dt_node_to_map()
889 dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", in sppctl_dt_node_to_map()
904 dev_dbg(pctldev->dev, "%s: IOP\n", in sppctl_dt_node_to_map()
907 /* A fully-pinmux pin */ in sppctl_dt_node_to_map()
912 dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, in sppctl_dt_node_to_map()
929 dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); in sppctl_dt_node_to_map()
942 dev_err(pctldev->dev, "Zero-func %d out of range!\n", in sppctl_dt_node_to_map()
948 switch (f->type) { in sppctl_dt_node_to_map()
951 dev_dbg(pctldev->dev, "%s: No map\n", f->name); in sppctl_dt_node_to_map()
955 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); in sppctl_dt_node_to_map()
956 dev_dbg(pctldev->dev, "%s: No map\n", f->name); in sppctl_dt_node_to_map()
960 dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", in sppctl_dt_node_to_map()
961 dt_fun, f->name); in sppctl_dt_node_to_map()
968 dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); in sppctl_dt_node_to_map()
977 return -ENOMEM; in sppctl_dt_node_to_map()
996 /* Calculate number of total group (GPIO + group-pinmux group). */ in sppctl_group_groups()
997 sppctl->unq_grps_sz = sppctl_gpio_list_sz; in sppctl_group_groups()
1000 sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; in sppctl_group_groups()
1002 sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, in sppctl_group_groups()
1003 sizeof(*sppctl->unq_grps), GFP_KERNEL); in sppctl_group_groups()
1004 if (!sppctl->unq_grps) in sppctl_group_groups()
1005 return -ENOMEM; in sppctl_group_groups()
1007 sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, in sppctl_group_groups()
1008 sizeof(*sppctl->g2fp_maps), GFP_KERNEL); in sppctl_group_groups()
1009 if (!sppctl->g2fp_maps) in sppctl_group_groups()
1010 return -ENOMEM; in sppctl_group_groups()
1014 sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; in sppctl_group_groups()
1015 sppctl->g2fp_maps[i].f_idx = 0; in sppctl_group_groups()
1016 sppctl->g2fp_maps[i].g_idx = i; in sppctl_group_groups()
1019 /* Add group-pinmux to end of GPIO pins. */ in sppctl_group_groups()
1026 sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; in sppctl_group_groups()
1027 sppctl->g2fp_maps[j].f_idx = i; in sppctl_group_groups()
1028 sppctl->g2fp_maps[j].g_idx = k; in sppctl_group_groups()
1041 sppctl->pctl_desc.owner = THIS_MODULE; in sppctl_pinctrl_init()
1042 sppctl->pctl_desc.name = dev_name(&pdev->dev); in sppctl_pinctrl_init()
1043 sppctl->pctl_desc.pins = sppctl_pins_all; in sppctl_pinctrl_init()
1044 sppctl->pctl_desc.npins = sppctl_pins_all_sz; in sppctl_pinctrl_init()
1045 sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; in sppctl_pinctrl_init()
1046 sppctl->pctl_desc.confops = &sppctl_pconf_ops; in sppctl_pinctrl_init()
1047 sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; in sppctl_pinctrl_init()
1053 err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, in sppctl_pinctrl_init()
1054 sppctl, &sppctl->pctl_dev); in sppctl_pinctrl_init()
1056 return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); in sppctl_pinctrl_init()
1058 pinctrl_enable(sppctl->pctl_dev); in sppctl_pinctrl_init()
1064 sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); in sppctl_resource_map()
1065 if (IS_ERR(sppctl->moon2_base)) in sppctl_resource_map()
1066 return PTR_ERR(sppctl->moon2_base); in sppctl_resource_map()
1068 sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); in sppctl_resource_map()
1069 if (IS_ERR(sppctl->gpioxt_base)) in sppctl_resource_map()
1070 return PTR_ERR(sppctl->gpioxt_base); in sppctl_resource_map()
1072 sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); in sppctl_resource_map()
1073 if (IS_ERR(sppctl->first_base)) in sppctl_resource_map()
1074 return PTR_ERR(sppctl->first_base); in sppctl_resource_map()
1076 sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); in sppctl_resource_map()
1077 if (IS_ERR(sppctl->moon1_base)) in sppctl_resource_map()
1078 return PTR_ERR(sppctl->moon1_base); in sppctl_resource_map()
1088 sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); in sppctl_probe()
1090 return -ENOMEM; in sppctl_probe()
1105 pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); in sppctl_probe()
1111 { .compatible = "sunplus,sp7021-pctl" },