39 	struct sh_pfc *pfc;  member
49 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
57 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
65 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
66 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
105 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
243 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
298 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
306 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
316 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
317 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
326 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
327 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
334 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
337 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
349 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
356 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
363 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
372 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
373 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
378 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
380 	if (!pfc->gpio && !cfg->mux_mark) {  in sh_pfc_gpio_request_enable()
384 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
386 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
396 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
406 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
407 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
411 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
415 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);  in sh_pfc_gpio_disable_free()
416 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
425 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
427 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
428 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
442 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
443 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
444 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
461 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,  in sh_pfc_pinconf_find_drive_strength_reg()  argument
468 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {  in sh_pfc_pinconf_find_drive_strength_reg()
484 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_get_drive_strength()  argument
492 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_get_drive_strength()
496 	val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);  in sh_pfc_pinconf_get_drive_strength()
504 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_set_drive_strength()  argument
514 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_set_drive_strength()
528 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
530 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_set_drive_strength()
534 	sh_pfc_write(pfc, reg, val);  in sh_pfc_pinconf_set_drive_strength()
536 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
542 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
545 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
546 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
573 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
578 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
587 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
590 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
591 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
592 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
604 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);  in sh_pfc_pinconf_get()
613 		int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_get()
614 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_get()
619 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_get()
622 		bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_get()
626 		val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_get()
648 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
656 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
663 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
666 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
667 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
668 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
677 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);  in sh_pfc_pinconf_set()
686 			int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_set()
687 			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_set()
692 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_set()
695 			bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_set()
706 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
707 			val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_set()
712 			sh_pfc_write(pfc, pocctrl, val);  in sh_pfc_pinconf_set()
713 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
735 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
736 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
756 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
761 	pmx->pins = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
762 				 pfc->info->nr_pins, sizeof(*pmx->pins),  in sh_pfc_map_pins()
767 	pmx->configs = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
768 				    pfc->info->nr_pins, sizeof(*pmx->configs),  in sh_pfc_map_pins()
773 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
774 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
785 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
790 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
794 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
796 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
806 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
808 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,  in sh_pfc_register_pinctrl()
811 		dev_err(pfc->dev, "could not register: %i\n", ret);  in sh_pfc_register_pinctrl()
839 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rcar_pinmux_get_bias()  argument
844 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_get_bias()
849 		if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))  in rcar_pinmux_get_bias()
851 		else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))  in rcar_pinmux_get_bias()
856 		if (sh_pfc_read(pfc, reg->pud) & BIT(bit))  in rcar_pinmux_get_bias()
863 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rcar_pinmux_set_bias()  argument
870 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_set_bias()
875 		enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);  in rcar_pinmux_set_bias()
880 				updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
884 				sh_pfc_write(pfc, reg->pud, updown);  in rcar_pinmux_set_bias()
887 		sh_pfc_write(pfc, reg->puen, enable);  in rcar_pinmux_set_bias()
889 		enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
893 		sh_pfc_write(pfc, reg->pud, enable);  in rcar_pinmux_set_bias()
902 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rmobile_pinmux_get_bias()  argument
904 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_get_bias()
905 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_get_bias()
919 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rmobile_pinmux_set_bias()  argument
922 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_set_bias()
923 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_set_bias()