pinctrl/renesas/pinctrl-rzv2m.c

1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinconf.h>
28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
31 #include "../pinconf.h"
34 #define DRV_NAME	"pinctrl-rzv2m"
42 #define MUX_FUNC(pinconf)	FIELD_GET(MUX_FUNC_MASK, (pinconf))
91 #define DRV(n)		((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \
148 	rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
149 	rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
152 	addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
156 	rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
157 	rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
172 		return -EINVAL;
175 		return -EINVAL;
177 	psel_val = func->data;
178 	pins = group->pins;
180 	for (i = 0; i < group->num_pins; i++) {
181 		dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
202 		return -ENOMEM;
204 	map->type = type;
205 	map->data.configs.group_or_pin = group_or_pin;
206 	map->data.configs.configs = cfgs;
207 	map->data.configs.num_configs = num_configs;
237 		num_pinmux = pinmux->length / sizeof(u32);
240 	if (ret == -EINVAL) {
243 		dev_err(pctrl->dev, "Invalid pins list in DT\n");
253 		dev_err(pctrl->dev,
255 		return -EINVAL;
263 		dev_err(pctrl->dev, "DT node must contain a config\n");
264 		ret = -ENODEV;
276 		ret = -ENOMEM;
296 	pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
297 	psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
299 	pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
301 		ret = -ENOMEM;
317 		name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
320 			ret = -ENOMEM;
324 		name = np->name;
327 	mutex_lock(&pctrl->mutex);
347 	mutex_unlock(&pctrl->mutex);
354 	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
361 	mutex_unlock(&pctrl->mutex);
418 	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
419 	ret = -EINVAL;
434 	if (bit >= pincount || port >= pctrl->data->n_port_pins)
435 		return -EINVAL;
437 	data = pctrl->data->port_pin_configs[port];
439 		return -EINVAL;
447 	void __iomem *addr = pctrl->base + offset;
451 	spin_lock_irqsave(&pctrl->lock, flags);
454 	spin_unlock_irqrestore(&pctrl->lock, flags);
463 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
464 	unsigned int *pin_data = pin->drv_data;
472 		return -EINVAL;
484 			return -EINVAL;
494 			return -EINVAL;
496 		/* PUPD uses 2-bits per pin */
499 		switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
511 			return -EINVAL;
517 			return -EINVAL;
519 		/* DRV uses 2-bits per pin */
522 		val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
539 			return -EINVAL;
546 			return -EINVAL;
548 		arg = readl(pctrl->base + SR(port)) & BIT(bit);
552 		return -ENOTSUPP;
566 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
567 	unsigned int *pin_data = pin->drv_data;
576 		return -EINVAL;
588 			return -EINVAL;
598 				return -EINVAL;
600 			/* PUPD uses 2-bits per pin */
623 				return -EINVAL;
640 				return -EINVAL;
648 				return -EINVAL;
650 			/* DRV uses 2-bits per pin */
653 			rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
661 				return -EINVAL;
663 			rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
668 			return -EOPNOTSUPP;
717 			return -EOPNOTSUPP;
757 	ret = pinctrl_gpio_request(chip->base + offset);
769 	rzv2m_writel_we(pctrl->base + OE(port), bit, output);
770 	rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
779 	if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
804 	rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
828 		return !!(readl(pctrl->base + DI(port)) & BIT(bit));
830 		return !!(readl(pctrl->base + DO(port)) & BIT(bit));
835 	pinctrl_gpio_free(chip->base + offset);
935 	struct device_node *np = pctrl->dev->of_node;
936 	struct gpio_chip *chip = &pctrl->gpio_chip;
937 	const char *name = dev_name(pctrl->dev);
941 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
943 		dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
950 	    of_args.args[2] != pctrl->data->n_port_pins) {
951 		dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
952 		return -EINVAL;
955 	chip->names = pctrl->data->port_pins;
956 	chip->request = rzv2m_gpio_request;
957 	chip->free = rzv2m_gpio_free;
958 	chip->get_direction = rzv2m_gpio_get_direction;
959 	chip->direction_input = rzv2m_gpio_direction_input;
960 	chip->direction_output = rzv2m_gpio_direction_output;
961 	chip->get = rzv2m_gpio_get;
962 	chip->set = rzv2m_gpio_set;
963 	chip->label = name;
964 	chip->parent = pctrl->dev;
965 	chip->owner = THIS_MODULE;
966 	chip->base = -1;
967 	chip->ngpio = of_args.args[2];
969 	pctrl->gpio_range.id = 0;
970 	pctrl->gpio_range.pin_base = 0;
971 	pctrl->gpio_range.base = 0;
972 	pctrl->gpio_range.npins = chip->ngpio;
973 	pctrl->gpio_range.name = chip->label;
974 	pctrl->gpio_range.gc = chip;
975 	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
977 		dev_err(pctrl->dev, "failed to add GPIO controller\n");
981 	dev_dbg(pctrl->dev, "Registered gpio controller\n");
993 	pctrl->desc.name = DRV_NAME;
994 	pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
995 	pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
996 	pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
997 	pctrl->desc.confops = &rzv2m_pinctrl_confops;
998 	pctrl->desc.owner = THIS_MODULE;
1000 	pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1002 		return -ENOMEM;
1004 	pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1007 		return -ENOMEM;
1009 	pctrl->pins = pins;
1010 	pctrl->desc.pins = pins;
1012 	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1014 		pins[i].name = pctrl->data->port_pins[i];
1017 		pin_data[i] = pctrl->data->port_pin_configs[j];
1021 	for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1022 		unsigned int index = pctrl->data->n_port_pins + i;
1025 		pins[index].name = pctrl->data->dedicated_pins[i].name;
1026 		pin_data[index] = pctrl->data->dedicated_pins[i].config;
1030 	ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1031 					     &pctrl->pctl);
1033 		dev_err(pctrl->dev, "pinctrl registration failed\n");
1037 	ret = pinctrl_enable(pctrl->pctl);
1039 		dev_err(pctrl->dev, "pinctrl enable failed\n");
1045 		dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1058 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1060 		return -ENOMEM;
1062 	pctrl->dev = &pdev->dev;
1064 	pctrl->data = of_device_get_match_data(&pdev->dev);
1065 	if (!pctrl->data)
1066 		return -EINVAL;
1068 	pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1069 	if (IS_ERR(pctrl->base))
1070 		return PTR_ERR(pctrl->base);
1072 	clk = devm_clk_get_enabled(pctrl->dev, NULL);
1074 		return dev_err_probe(pctrl->dev, PTR_ERR(clk),
1077 	spin_lock_init(&pctrl->lock);
1078 	mutex_init(&pctrl->mutex);
1086 	dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1100 		.compatible = "renesas,r9a09g011-pinctrl",