Lines Matching +full:pin +full:-
1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
11 * This includes SoCs which are sub- or super- sets of this particular line,
22 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
69 /* Pin mux flags */
74 /* ----------------------------------------------------------------------------
79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
82 u8 pin: 4; member
87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
96 * rza1_swio_pin - describe a single pin that needs swio flag applied.
99 u16 pin: 4; member
106 * rza1_swio_entry - describe a list of pins that needs swio flag applied
114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
121 /* ----------------------------------------------------------------------------
126 { .pin = 0, .func = 1 },
127 { .pin = 1, .func = 1 },
128 { .pin = 2, .func = 1 },
129 { .pin = 3, .func = 1 },
130 { .pin = 4, .func = 1 },
131 { .pin = 5, .func = 1 },
132 { .pin = 6, .func = 1 },
133 { .pin = 7, .func = 1 },
137 { .pin = 0, .func = 1 },
138 { .pin = 1, .func = 1 },
139 { .pin = 2, .func = 1 },
140 { .pin = 3, .func = 1 },
141 { .pin = 4, .func = 1 },
142 { .pin = 0, .func = 4 },
143 { .pin = 1, .func = 4 },
144 { .pin = 2, .func = 4 },
145 { .pin = 3, .func = 4 },
146 { .pin = 5, .func = 1 },
147 { .pin = 6, .func = 1 },
148 { .pin = 7, .func = 1 },
149 { .pin = 8, .func = 1 },
150 { .pin = 9, .func = 1 },
151 { .pin = 10, .func = 1 },
152 { .pin = 11, .func = 1 },
153 { .pin = 12, .func = 1 },
154 { .pin = 13, .func = 1 },
155 { .pin = 14, .func = 1 },
156 { .pin = 15, .func = 1 },
157 { .pin = 12, .func = 4 },
158 { .pin = 13, .func = 4 },
159 { .pin = 14, .func = 4 },
160 { .pin = 15, .func = 4 },
164 { .pin = 3, .func = 2 },
165 { .pin = 10, .func = 7 },
166 { .pin = 11, .func = 7 },
167 { .pin = 13, .func = 7 },
168 { .pin = 14, .func = 7 },
169 { .pin = 15, .func = 7 },
170 { .pin = 10, .func = 8 },
171 { .pin = 11, .func = 8 },
172 { .pin = 13, .func = 8 },
173 { .pin = 14, .func = 8 },
174 { .pin = 15, .func = 8 },
178 { .pin = 0, .func = 8 },
179 { .pin = 1, .func = 8 },
180 { .pin = 2, .func = 8 },
181 { .pin = 3, .func = 8 },
182 { .pin = 10, .func = 3 },
183 { .pin = 11, .func = 3 },
184 { .pin = 13, .func = 3 },
185 { .pin = 14, .func = 3 },
186 { .pin = 15, .func = 3 },
187 { .pin = 10, .func = 4 },
188 { .pin = 11, .func = 4 },
189 { .pin = 13, .func = 4 },
190 { .pin = 14, .func = 4 },
191 { .pin = 15, .func = 4 },
192 { .pin = 12, .func = 5 },
193 { .pin = 13, .func = 5 },
194 { .pin = 14, .func = 5 },
195 { .pin = 15, .func = 5 },
199 { .pin = 0, .func = 1 },
200 { .pin = 1, .func = 1 },
201 { .pin = 2, .func = 1 },
202 { .pin = 3, .func = 1 },
203 { .pin = 4, .func = 1 },
204 { .pin = 5, .func = 1 },
205 { .pin = 6, .func = 1 },
206 { .pin = 7, .func = 1 },
207 { .pin = 8, .func = 1 },
208 { .pin = 9, .func = 1 },
209 { .pin = 10, .func = 1 },
210 { .pin = 11, .func = 1 },
211 { .pin = 12, .func = 1 },
212 { .pin = 13, .func = 1 },
213 { .pin = 14, .func = 1 },
214 { .pin = 15, .func = 1 },
218 { .pin = 13, .func = 3 },
222 { .pin = 8, .func = 3 },
223 { .pin = 9, .func = 3 },
224 { .pin = 10, .func = 3 },
225 { .pin = 11, .func = 3 },
226 { .pin = 14, .func = 2 },
227 { .pin = 15, .func = 2 },
228 { .pin = 14, .func = 3 },
229 { .pin = 15, .func = 3 },
233 { .pin = 0, .func = 2 },
234 { .pin = 1, .func = 2 },
235 { .pin = 4, .func = 2 },
236 { .pin = 5, .func = 2 },
237 { .pin = 6, .func = 2 },
238 { .pin = 7, .func = 2 },
242 { .pin = 6, .func = 2 },
243 { .pin = 7, .func = 2 },
244 { .pin = 9, .func = 2 },
245 { .pin = 6, .func = 4 },
246 { .pin = 7, .func = 4 },
247 { .pin = 9, .func = 4 },
248 { .pin = 10, .func = 2 },
249 { .pin = 11, .func = 2 },
250 { .pin = 10, .func = 4 },
251 { .pin = 11, .func = 4 },
252 { .pin = 12, .func = 4 },
253 { .pin = 13, .func = 4 },
254 { .pin = 14, .func = 4 },
255 { .pin = 15, .func = 4 },
259 { .port = 2, .pin = 7, .func = 4, .input = 0 },
260 { .port = 2, .pin = 11, .func = 4, .input = 0 },
261 { .port = 3, .pin = 7, .func = 3, .input = 0 },
262 { .port = 3, .pin = 7, .func = 8, .input = 0 },
263 { .port = 4, .pin = 7, .func = 5, .input = 0 },
264 { .port = 4, .pin = 7, .func = 11, .input = 0 },
265 { .port = 4, .pin = 15, .func = 6, .input = 0 },
266 { .port = 5, .pin = 0, .func = 1, .input = 1 },
267 { .port = 5, .pin = 1, .func = 1, .input = 1 },
268 { .port = 5, .pin = 2, .func = 1, .input = 1 },
269 { .port = 5, .pin = 3, .func = 1, .input = 1 },
270 { .port = 5, .pin = 4, .func = 1, .input = 1 },
271 { .port = 5, .pin = 5, .func = 1, .input = 1 },
272 { .port = 5, .pin = 6, .func = 1, .input = 1 },
273 { .port = 5, .pin = 7, .func = 1, .input = 1 },
274 { .port = 7, .pin = 4, .func = 6, .input = 0 },
275 { .port = 7, .pin = 11, .func = 2, .input = 0 },
276 { .port = 8, .pin = 10, .func = 8, .input = 0 },
277 { .port = 10, .pin = 15, .func = 2, .input = 0 },
302 /* ----------------------------------------------------------------------------
307 { .pin = 0, .func = 1 },
308 { .pin = 1, .func = 1 },
309 { .pin = 2, .func = 1 },
310 { .pin = 3, .func = 1 },
311 { .pin = 4, .func = 1 },
312 { .pin = 5, .func = 1 },
313 { .pin = 6, .func = 1 },
314 { .pin = 7, .func = 1 },
318 { .pin = 0, .func = 2 },
319 { .pin = 1, .func = 2 },
320 { .pin = 2, .func = 2 },
321 { .pin = 4, .func = 2 },
322 { .pin = 5, .func = 2 },
323 { .pin = 10, .func = 2 },
324 { .pin = 11, .func = 2 },
325 { .pin = 12, .func = 2 },
326 { .pin = 13, .func = 2 },
330 { .pin = 1, .func = 4 },
331 { .pin = 2, .func = 2 },
332 { .pin = 3, .func = 2 },
333 { .pin = 6, .func = 2 },
334 { .pin = 7, .func = 2 },
338 { .pin = 0, .func = 1 },
339 { .pin = 1, .func = 1 },
340 { .pin = 2, .func = 1 },
341 { .pin = 3, .func = 1 },
342 { .pin = 4, .func = 1 },
343 { .pin = 5, .func = 1 },
344 { .pin = 6, .func = 1 },
345 { .pin = 7, .func = 1 },
346 { .pin = 8, .func = 1 },
347 { .pin = 9, .func = 1 },
348 { .pin = 10, .func = 1 },
349 { .pin = 11, .func = 1 },
350 { .pin = 12, .func = 1 },
351 { .pin = 13, .func = 1 },
352 { .pin = 14, .func = 1 },
353 { .pin = 15, .func = 1 },
354 { .pin = 0, .func = 2 },
355 { .pin = 1, .func = 2 },
356 { .pin = 2, .func = 2 },
357 { .pin = 3, .func = 2 },
361 { .pin = 0, .func = 1 },
362 { .pin = 1, .func = 1 },
363 { .pin = 2, .func = 1 },
364 { .pin = 3, .func = 1 },
365 { .pin = 4, .func = 1 },
366 { .pin = 5, .func = 1 },
367 { .pin = 6, .func = 1 },
368 { .pin = 7, .func = 1 },
369 { .pin = 8, .func = 1 },
370 { .pin = 9, .func = 1 },
371 { .pin = 10, .func = 1 },
372 { .pin = 11, .func = 1 },
373 { .pin = 12, .func = 1 },
374 { .pin = 13, .func = 1 },
375 { .pin = 14, .func = 1 },
376 { .pin = 15, .func = 1 },
380 { .pin = 2, .func = 2 },
381 { .pin = 3, .func = 2 },
382 { .pin = 5, .func = 2 },
383 { .pin = 6, .func = 2 },
384 { .pin = 7, .func = 2 },
385 { .pin = 2, .func = 3 },
386 { .pin = 3, .func = 3 },
387 { .pin = 5, .func = 3 },
388 { .pin = 6, .func = 3 },
389 { .pin = 7, .func = 3 },
393 { .pin = 1, .func = 2 },
394 { .pin = 0, .func = 3 },
395 { .pin = 1, .func = 3 },
396 { .pin = 3, .func = 3 },
397 { .pin = 4, .func = 3 },
398 { .pin = 5, .func = 3 },
402 { .port = 2, .pin = 8, .func = 2, .input = 0 },
403 { .port = 5, .pin = 6, .func = 3, .input = 0 },
404 { .port = 6, .pin = 6, .func = 3, .input = 0 },
405 { .port = 6, .pin = 10, .func = 3, .input = 0 },
406 { .port = 7, .pin = 10, .func = 2, .input = 0 },
407 { .port = 8, .pin = 2, .func = 3, .input = 0 },
430 /* ----------------------------------------------------------------------------
434 * struct rza1_mux_conf - describes a pin multiplexing operation
436 * @id: the pin identifier from 0 to RZA1_NPINS
437 * @port: the port where pin sits on
438 * @pin: pin id
441 * @value: output value to set the pin to
446 u8 pin; member
453 * struct rza1_port - describes a pin port
455 * This is mostly useful to lock register writes per-bank and not globally.
470 * struct rza1_pinctrl - RZ pincontroller device
475 * @nport: number of pin controller ports
476 * @ports: pin controller banks
477 * @pins: pin array for pinctrl core
499 /* ----------------------------------------------------------------------------
503 unsigned int pin, in rza1_pinmux_get_bidir() argument
511 for (i = 0; i < entry->npins; ++i) { in rza1_pinmux_get_bidir()
512 bidir_pin = &entry->pins[i]; in rza1_pinmux_get_bidir()
513 if (bidir_pin->pin == pin && bidir_pin->func == func) in rza1_pinmux_get_bidir()
521 unsigned int pin, in rza1_pinmux_get_swio() argument
529 for (i = 0; i < table->npins; ++i) { in rza1_pinmux_get_swio()
530 swio_pin = &table->pins[i]; in rza1_pinmux_get_swio()
531 if (swio_pin->port == port && swio_pin->pin == pin && in rza1_pinmux_get_swio()
532 swio_pin->func == func) in rza1_pinmux_get_swio()
533 return swio_pin->input; in rza1_pinmux_get_swio()
536 return -ENOENT; in rza1_pinmux_get_swio()
540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
542 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, in rza1_pinmux_get_flags() argument
547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; in rza1_pinmux_get_flags()
548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; in rza1_pinmux_get_flags()
549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; in rza1_pinmux_get_flags()
553 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries)) in rza1_pinmux_get_flags()
556 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries); in rza1_pinmux_get_flags()
565 /* ----------------------------------------------------------------------------
570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_set_bit()
590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_get_bit()
596 * rza1_pin_reset() - reset a pin to default initial state
598 * Reset pin state disabling input buffer and bi-directional control,
600 * Note that pin is now configured with direction as input but with input
601 * buffer disabled. This implies the pin value cannot be read in this state.
603 * @port: port where pin sits on
604 * @pin: pin offset
606 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) in rza1_pin_reset() argument
610 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_reset()
611 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0); in rza1_pin_reset()
612 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); in rza1_pin_reset()
614 rza1_set_bit(port, RZA1_PM_REG, pin, 1); in rza1_pin_reset()
615 rza1_set_bit(port, RZA1_PMC_REG, pin, 0); in rza1_pin_reset()
616 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0); in rza1_pin_reset()
617 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_reset()
621 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
624 * pin value from PPR.
626 * @port: port where pin sits on
627 * @pin: pin offset
631 unsigned int pin, bool input) in rza1_pin_set_direction() argument
635 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set_direction()
637 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1); in rza1_pin_set_direction()
639 rza1_set_bit(port, RZA1_PM_REG, pin, 1); in rza1_pin_set_direction()
640 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); in rza1_pin_set_direction()
642 rza1_set_bit(port, RZA1_PM_REG, pin, 0); in rza1_pin_set_direction()
643 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); in rza1_pin_set_direction()
646 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set_direction()
649 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, in rza1_pin_set() argument
654 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set()
655 rza1_set_bit(port, RZA1_P_REG, pin, !!value); in rza1_pin_set()
656 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set()
659 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) in rza1_pin_get() argument
661 return rza1_get_bit(port, RZA1_PPR_REG, pin); in rza1_pin_get()
665 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
667 * @rza1_pctl: RZ/A1 pin controller device
668 * @mux_conf: pin multiplexing descriptor
673 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; in rza1_pin_mux_single()
674 unsigned int pin = mux_conf->pin; in rza1_pin_mux_single() local
675 u8 mux_func = mux_conf->mux_func; in rza1_pin_mux_single()
676 u8 mux_flags = mux_conf->mux_flags; in rza1_pin_mux_single()
679 rza1_pin_reset(port, pin); in rza1_pin_mux_single()
682 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, in rza1_pin_mux_single()
690 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); in rza1_pin_mux_single()
695 * Be careful here: the pin mux sub-nodes in device tree in rza1_pin_mux_single()
700 * ---------------------------------------------------- in rza1_pin_mux_single()
703 * PMC PFC PFCE PFCAE (mux_func - 1) in rza1_pin_mux_single()
712 * ---------------------------------------------------- in rza1_pin_mux_single()
714 mux_func -= 1; in rza1_pin_mux_single()
715 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK); in rza1_pin_mux_single()
716 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK); in rza1_pin_mux_single()
717 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK); in rza1_pin_mux_single()
722 * to I/O direction specified by pin configuration -after- PMC has been in rza1_pin_mux_single()
726 rza1_set_bit(port, RZA1_PM_REG, pin, in rza1_pin_mux_single()
729 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1); in rza1_pin_mux_single()
731 rza1_set_bit(port, RZA1_PMC_REG, pin, 1); in rza1_pin_mux_single()
736 /* ----------------------------------------------------------------------------
741 * rza1_gpio_request() - configure pin in port mode
743 * Configure a pin as gpio (port mode).
744 * After reset, the pin is in input mode with input buffer disabled.
745 * To use the pin as input or output, set_direction shall be called first
760 * rza1_gpio_free() - reset a pin
763 * Reset pin to port mode, with input buffer disabled. This overwrites all
802 /* Set value before driving pin direction */ in rza1_gpio_direction_output()
810 * rza1_gpio_get() - read a gpio pin value
812 * Read gpio pin value through PPR register.
813 * Requires bi-directional mode to work when reading the value of a pin
843 /* ----------------------------------------------------------------------------
848 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
849 * children sub-nodes
861 return of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
868 return -EINVAL; in rza1_dt_node_pin_count()
871 npins += of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
878 * rza1_parse_pinmux_node() - parse a pin mux sub-node
880 * @rza1_pctl: RZ/A1 pin controller device
881 * @np: of pmx sub-node
882 * @mux_confs: array of pin mux configurations to fill with parsed info
883 * @grpins: array of pin ids to mux
890 struct pinctrl_dev *pctldev = rza1_pctl->pctl; in rza1_parse_pinmux_node()
902 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); in rza1_parse_pinmux_node()
903 return -ENOENT; in rza1_parse_pinmux_node()
905 npins = of_pins->length / sizeof(u32); in rza1_parse_pinmux_node()
908 * Collect pin configuration properties: they apply to all pins in in rza1_parse_pinmux_node()
909 * this sub-node in rza1_parse_pinmux_node()
914 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
915 "Unable to parse pin configuration options for %pOFn\n", in rza1_parse_pinmux_node()
921 * Create a mask with pinmux flags from pin configuration; in rza1_parse_pinmux_node()
922 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction in rza1_parse_pinmux_node()
942 /* Collect pin positions and their mux settings. */ in rza1_parse_pinmux_node()
951 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; in rza1_parse_pinmux_node()
952 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); in rza1_parse_pinmux_node()
953 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); in rza1_parse_pinmux_node()
954 mux_conf->mux_func = MUX_FUNC(of_pinconf); in rza1_parse_pinmux_node()
955 mux_conf->mux_flags = pinmux_flags; in rza1_parse_pinmux_node()
957 if (mux_conf->port >= RZA1_NPORTS || in rza1_parse_pinmux_node()
958 mux_conf->pin >= RZA1_PINS_PER_PORT) { in rza1_parse_pinmux_node()
959 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
960 "Wrong port %u pin %u for %s property\n", in rza1_parse_pinmux_node()
961 mux_conf->port, mux_conf->pin, prop_name); in rza1_parse_pinmux_node()
962 return -EINVAL; in rza1_parse_pinmux_node()
965 grpins[i] = mux_conf->id; in rza1_parse_pinmux_node()
972 * rza1_dt_node_to_map() - map a pin mux node to a function/group
974 * Parse and register a pin mux function.
976 * @pctldev: pin controller device
978 * @map: pointer to pin map (output)
997 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); in rza1_dt_node_to_map()
998 return -EINVAL; in rza1_dt_node_to_map()
1003 * in fact, functions and groups are identical for this pin controller in rza1_dt_node_to_map()
1004 * except that functions carry an array of per-pin mux configuration in rza1_dt_node_to_map()
1007 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), in rza1_dt_node_to_map()
1009 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), in rza1_dt_node_to_map()
1011 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); in rza1_dt_node_to_map()
1014 return -ENOMEM; in rza1_dt_node_to_map()
1018 * If the node does not contain "pinmux" property (-ENOENT) in rza1_dt_node_to_map()
1019 * that property shall be specified in all its children sub-nodes. in rza1_dt_node_to_map()
1025 if (ret == -ENOENT) in rza1_dt_node_to_map()
1040 /* Register pin group and function name to pinctrl_generic */ in rza1_dt_node_to_map()
1041 grpname = np->name; in rza1_dt_node_to_map()
1044 mutex_lock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1048 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1059 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", in rza1_dt_node_to_map()
1066 ret = -ENOMEM; in rza1_dt_node_to_map()
1070 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in rza1_dt_node_to_map()
1071 (*map)->data.mux.group = np->name; in rza1_dt_node_to_map()
1072 (*map)->data.mux.function = np->name; in rza1_dt_node_to_map()
1074 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1083 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1085 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", in rza1_dt_node_to_map()
1105 /* ----------------------------------------------------------------------------
1110 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1112 * @pctldev: pin controller device
1127 return -EINVAL; in rza1_set_mux()
1131 return -EINVAL; in rza1_set_mux()
1133 mux_confs = (struct rza1_mux_conf *)func->data; in rza1_set_mux()
1134 for (i = 0; i < grp->num_pins; ++i) { in rza1_set_mux()
1153 /* ----------------------------------------------------------------------------
1154 * RZ/A1 pin controller driver operations
1158 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1160 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1163 * @rza1_pctl: RZ/A1 pin controller device
1164 * @fwnode: gpio-controller firmware node
1166 * @range: pin range to register to pinctrl core
1173 const char *list_name = "gpio-ranges"; in rza1_parse_gpiochip()
1181 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", in rza1_parse_gpiochip()
1187 * Find out on which port this gpio-chip maps to by inspecting the in rza1_parse_gpiochip()
1188 * second argument of the "gpio-ranges" property. in rza1_parse_gpiochip()
1193 dev_err(rza1_pctl->dev, in rza1_parse_gpiochip()
1195 return -EINVAL; in rza1_parse_gpiochip()
1199 chip->base = -1; in rza1_parse_gpiochip()
1200 chip->ngpio = args.args[2]; in rza1_parse_gpiochip()
1201 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode); in rza1_parse_gpiochip()
1202 if (!chip->label) in rza1_parse_gpiochip()
1203 return -ENOMEM; in rza1_parse_gpiochip()
1205 chip->fwnode = fwnode; in rza1_parse_gpiochip()
1206 chip->parent = rza1_pctl->dev; in rza1_parse_gpiochip()
1208 range->id = gpioport; in rza1_parse_gpiochip()
1209 range->name = chip->label; in rza1_parse_gpiochip()
1210 range->pin_base = range->base = pinctrl_base; in rza1_parse_gpiochip()
1211 range->npins = args.args[2]; in rza1_parse_gpiochip()
1212 range->gc = chip; in rza1_parse_gpiochip()
1214 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, in rza1_parse_gpiochip()
1215 &rza1_pctl->ports[gpioport]); in rza1_parse_gpiochip()
1219 pinctrl_add_gpio_range(rza1_pctl->pctl, range); in rza1_parse_gpiochip()
1221 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", in rza1_parse_gpiochip()
1222 chip->label, chip->ngpio); in rza1_parse_gpiochip()
1228 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1230 * @rza1_pctl: RZ/A1 pin controller device
1241 ngpiochips = gpiochip_node_count(rza1_pctl->dev); in rza1_gpio_register()
1243 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); in rza1_gpio_register()
1247 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1249 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1252 return -ENOMEM; in rza1_gpio_register()
1255 for_each_gpiochip_node(rza1_pctl->dev, child) { in rza1_gpio_register()
1266 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); in rza1_gpio_register()
1272 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1275 * @rza1_pctl: RZ/A1 pin controller device
1284 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), in rza1_pinctrl_register()
1286 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), in rza1_pinctrl_register()
1289 return -ENOMEM; in rza1_pinctrl_register()
1291 rza1_pctl->pins = pins; in rza1_pinctrl_register()
1292 rza1_pctl->desc.pins = pins; in rza1_pinctrl_register()
1293 rza1_pctl->desc.npins = RZA1_NPINS; in rza1_pinctrl_register()
1294 rza1_pctl->ports = ports; in rza1_pinctrl_register()
1297 unsigned int pin = RZA1_PIN_ID_TO_PIN(i); in rza1_pinctrl_register() local
1301 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, in rza1_pinctrl_register()
1302 "P%u-%u", port, pin); in rza1_pinctrl_register()
1304 return -ENOMEM; in rza1_pinctrl_register()
1309 * they provide per-port lock and logical base address. in rza1_pinctrl_register()
1314 ports[port_id].base = rza1_pctl->base; in rza1_pinctrl_register()
1320 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, in rza1_pinctrl_register()
1321 rza1_pctl, &rza1_pctl->pctl); in rza1_pinctrl_register()
1323 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1324 "RZ/A1 pin controller registration failed\n"); in rza1_pinctrl_register()
1328 ret = pinctrl_enable(rza1_pctl->pctl); in rza1_pinctrl_register()
1330 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1331 "RZ/A1 pin controller failed to start\n"); in rza1_pinctrl_register()
1337 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); in rza1_pinctrl_register()
1349 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); in rza1_pinctrl_probe()
1351 return -ENOMEM; in rza1_pinctrl_probe()
1353 rza1_pctl->dev = &pdev->dev; in rza1_pinctrl_probe()
1355 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); in rza1_pinctrl_probe()
1356 if (IS_ERR(rza1_pctl->base)) in rza1_pinctrl_probe()
1357 return PTR_ERR(rza1_pctl->base); in rza1_pinctrl_probe()
1359 mutex_init(&rza1_pctl->mutex); in rza1_pinctrl_probe()
1363 rza1_pctl->desc.name = DRIVER_NAME; in rza1_pinctrl_probe()
1364 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; in rza1_pinctrl_probe()
1365 rza1_pctl->desc.pmxops = &rza1_pinmux_ops; in rza1_pinctrl_probe()
1366 rza1_pctl->desc.owner = THIS_MODULE; in rza1_pinctrl_probe()
1367 rza1_pctl->data = of_device_get_match_data(&pdev->dev); in rza1_pinctrl_probe()
1373 dev_info(&pdev->dev, in rza1_pinctrl_probe()
1374 "RZ/A1 pin controller and gpio successfully registered\n"); in rza1_pinctrl_probe()
1382 .compatible = "renesas,r7s72100-ports",
1387 .compatible = "renesas,r7s72102-ports",
1408 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");