Lines Matching refs:PINMUX_IPSR_MSEL
427 PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0),
428 PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0),
429 PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0),
433 PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0),
434 PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0),
435 PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0),
439 PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0),
440 PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0),
441 PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0),
442 PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0),
446 PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0),
447 PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0),
448 PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0),
449 PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0),
450 PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0),
451 PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0),
455 PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0),
456 PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0),
457 PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0),
458 PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0),
459 PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0),
463 PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0),
464 PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0),
465 PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0),
469 PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0),
470 PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0),
471 PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0),
475 PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0),
476 PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0),
477 PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0),