Lines Matching refs:PINMUX_IPSR_MSEL
944 PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
945 PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
949 PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
950 PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
954 PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
955 PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
956 PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
960 PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
961 PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
962 PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
963 PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
964 PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
968 PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
969 PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
970 PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
971 PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
972 PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
976 PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
977 PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
978 PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
979 PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
980 PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
984 PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
985 PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
986 PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
987 PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
988 PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
992 PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
993 PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
994 PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
995 PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
996 PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
1000 PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
1001 PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
1002 PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
1003 PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
1007 PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
1008 PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
1009 PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
1010 PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
1014 PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
1015 PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
1016 PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
1017 PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
1021 PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
1022 PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
1023 PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
1027 PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
1028 PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
1029 PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
1030 PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
1034 PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
1035 PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
1036 PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
1037 PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),