Lines Matching refs:pctrl
63 struct pinctrl_dev *pctrl; member
86 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
91 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
103 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, in MSM_ACCESSOR()
108 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_groups_count() local
115 return pctrl->soc->ngroups; in msm_get_groups_count()
121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
133 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
134 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
148 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
149 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
156 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
158 return pctrl->soc->nfunctions; in msm_get_functions_count()
164 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
166 return pctrl->soc->functions[function].name; in msm_get_function_name()
174 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
176 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
177 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
185 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
186 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
189 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
190 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
196 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
218 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
221 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
223 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
232 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
233 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
237 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
240 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
255 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
257 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
260 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
265 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
268 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
280 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
281 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
287 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
299 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
353 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
361 g = &pctrl->soc->groups[group]; in msm_config_group_get()
363 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
367 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
383 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
391 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
414 val = msm_readl_io(pctrl, g); in msm_config_group_get()
436 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
446 g = &pctrl->soc->groups[group]; in msm_config_group_set()
452 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
465 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
471 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
490 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
491 val = msm_readl_io(pctrl, g); in msm_config_group_set()
496 msm_writel_io(val, pctrl, g); in msm_config_group_set()
497 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
534 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
541 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
545 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
546 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
549 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
550 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
565 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
569 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
571 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
573 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
575 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
577 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
585 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
589 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
591 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
593 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
598 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
600 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
602 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
604 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
611 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
615 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
617 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
626 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
629 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
631 val = msm_readl_io(pctrl, g); in msm_gpio_get()
638 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
642 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
644 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
646 val = msm_readl_io(pctrl, g); in msm_gpio_set()
651 msm_writel_io(val, pctrl, g); in msm_gpio_set()
653 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
665 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
690 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
691 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
692 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
699 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
715 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
739 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
742 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
749 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
759 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
770 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
772 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
816 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
825 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
827 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
829 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
831 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
832 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
836 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
843 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
851 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
854 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
856 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
858 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
883 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
885 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
887 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
893 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_unmask() local
901 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
904 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
906 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
908 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
911 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
913 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
915 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
921 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
928 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
935 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
940 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
958 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
959 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
965 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
978 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
989 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
995 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
999 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1000 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1005 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1007 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1009 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
1011 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1012 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1014 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1029 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
1032 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1033 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1039 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
1047 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1056 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1057 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1062 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1064 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1070 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1072 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1081 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1082 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1091 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1095 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1098 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1106 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1155 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1163 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1165 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1166 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1168 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1181 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1189 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1192 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1198 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1204 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1242 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1244 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1253 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1255 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1265 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1277 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1278 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1279 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1299 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1306 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1307 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1317 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1319 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1322 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1345 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1350 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1357 chip = &pctrl->chip; in msm_gpio_init()
1360 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1361 chip->parent = pctrl->dev; in msm_gpio_init()
1363 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1366 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1379 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1380 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1381 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1388 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1390 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1396 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1398 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1400 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1414 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1415 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1416 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1418 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1419 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1430 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1432 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1444 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1447 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1449 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1451 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1452 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1453 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1454 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1456 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1464 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1466 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1471 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1473 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1484 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1489 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1490 if (!pctrl) in msm_pinctrl_probe()
1493 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1494 pctrl->soc = soc_data; in msm_pinctrl_probe()
1495 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1496 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1497 pctrl->dev->of_node, in msm_pinctrl_probe()
1500 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1506 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1507 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1508 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1511 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1512 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1513 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1515 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1518 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1520 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1521 if (pctrl->irq < 0) in msm_pinctrl_probe()
1522 return pctrl->irq; in msm_pinctrl_probe()
1524 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1525 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1526 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1527 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1528 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1529 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1530 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1532 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1533 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1535 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1538 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1542 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1552 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1554 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1556 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()