87 			    const struct msm_pingroup *g) \
89 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 			      const struct msm_pingroup *g) \
94 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 				const struct msm_pingroup *g)  in MSM_ACCESSOR()
106 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;  in MSM_ACCESSOR()
108 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
191 	const struct msm_pingroup *g;  in msm_pinmux_set_mux()  local
196 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
197 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);  in msm_pinmux_set_mux()
199 	for (i = 0; i < g->nfuncs; i++) {  in msm_pinmux_set_mux()
200 		if (g->funcs[i] == function)  in msm_pinmux_set_mux()
204 	if (WARN_ON(i == g->nfuncs))  in msm_pinmux_set_mux()
223 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
231 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&  in msm_pinmux_set_mux()
233 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
235 		if (io_val & BIT(g->in_bit)) {  in msm_pinmux_set_mux()
236 			if (!(io_val & BIT(g->out_bit)))  in msm_pinmux_set_mux()
237 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
239 			if (io_val & BIT(g->out_bit))  in msm_pinmux_set_mux()
240 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
245 		if (val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
246 			val &= ~BIT(g->egpio_enable);  in msm_pinmux_set_mux()
249 		val |= i << g->mux_bit;  in msm_pinmux_set_mux()
251 		if (egpio_func && val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
252 			val |= BIT(g->egpio_enable);  in msm_pinmux_set_mux()
255 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
268 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
281 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()  local
284 	if (!g->nfuncs)  in msm_pinmux_request_gpio()
287 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
300 			  const struct msm_pingroup *g,  in msm_config_reg()  argument
310 		*bit = g->pull_bit;  in msm_config_reg()
312 		if (g->i2c_pull_bit)  in msm_config_reg()
313 			*mask |= BIT(g->i2c_pull_bit) >> *bit;  in msm_config_reg()
316 		*bit = g->od_bit;  in msm_config_reg()
320 		*bit = g->drv_bit;  in msm_config_reg()
326 		*bit = g->oe_bit;  in msm_config_reg()
352 	const struct msm_pingroup *g;  in msm_config_group_get()  local
361 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
363 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
367 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
393 		else if (arg & BIT(g->i2c_pull_bit))  in msm_config_group_get()
414 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
415 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
435 	const struct msm_pingroup *g;  in msm_config_group_set()  local
446 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
452 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
473 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)  in msm_config_group_set()
474 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;  in msm_config_group_set()
491 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
493 				val |= BIT(g->out_bit);  in msm_config_group_set()
495 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
496 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
546 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
549 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
564 	const struct msm_pingroup *g;  in msm_gpio_direction_input()  local
569 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
573 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
574 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
575 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
584 	const struct msm_pingroup *g;  in msm_gpio_direction_output()  local
589 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
593 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
595 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
597 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
598 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
600 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
601 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
602 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
612 	const struct msm_pingroup *g;  in msm_gpio_get_direction()  local
615 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
617 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
619 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :  in msm_gpio_get_direction()
625 	const struct msm_pingroup *g;  in msm_gpio_get()  local
629 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
631 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
632 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
637 	const struct msm_pingroup *g;  in msm_gpio_set()  local
642 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
646 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
648 		val |= BIT(g->out_bit);  in msm_gpio_set()
650 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
651 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
664 	const struct msm_pingroup *g;  in msm_gpio_dbg_show_one()  local
690 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
691 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
692 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
694 	is_out = !!(ctl_reg & BIT(g->oe_bit));  in msm_gpio_dbg_show_one()
695 	func = (ctl_reg >> g->mux_bit) & 7;  in msm_gpio_dbg_show_one()
696 	drive = (ctl_reg >> g->drv_bit) & 7;  in msm_gpio_dbg_show_one()
697 	pull = (ctl_reg >> g->pull_bit) & 3;  in msm_gpio_dbg_show_one()
699 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
700 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));  in msm_gpio_dbg_show_one()
703 		val = !!(io_reg & BIT(g->out_bit));  in msm_gpio_dbg_show_one()
705 		val = !!(io_reg & BIT(g->in_bit));  in msm_gpio_dbg_show_one()
708 		seq_printf(s, " %-8s: egpio\n", g->grp.name);  in msm_gpio_dbg_show_one()
712 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");  in msm_gpio_dbg_show_one()
817 					  const struct msm_pingroup *g,  in msm_gpio_update_dual_edge_pos()  argument
825 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
827 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
828 		pol ^= BIT(g->intr_polarity_bit);  in msm_gpio_update_dual_edge_pos()
829 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
831 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
832 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
844 	const struct msm_pingroup *g;  in msm_gpio_irq_mask()  local
854 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
858 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
880 		val &= ~BIT(g->intr_raw_status_bit);  in msm_gpio_irq_mask()
882 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
883 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
894 	const struct msm_pingroup *g;  in msm_gpio_irq_unmask()  local
904 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
908 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
909 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_unmask()
910 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
911 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
959 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()  local
965 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
978 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
996 	const struct msm_pingroup *g;  in msm_gpio_irq_ack()  local
1005 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
1009 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
1012 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1040 	const struct msm_pingroup *g;  in msm_gpio_irq_set_type()  local
1062 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1069 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)  in msm_gpio_irq_set_type()
1078 	if (g->intr_target_width)  in msm_gpio_irq_set_type()
1079 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);  in msm_gpio_irq_set_type()
1082 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1086 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1087 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1095 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1096 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1097 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1098 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1106 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1107 	was_enabled = val & BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1108 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1109 	if (g->intr_detection_width == 2) {  in msm_gpio_irq_set_type()
1110 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1111 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1114 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1115 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1118 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1119 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1122 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1123 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1128 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1131 	} else if (g->intr_detection_width == 1) {  in msm_gpio_irq_set_type()
1132 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1133 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1136 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1137 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1140 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1143 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1144 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1149 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1155 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1163 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1166 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1264 	const struct msm_pingroup *g;  in msm_gpio_irq_handler()  local
1278 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1279 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1280 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()