Lines Matching +full:function +full:- +full:mask
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
44 * @mask: mask
49 unsigned mask; member
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
59 * @mask: mask bits in the register value
66 unsigned mask; member
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
84 * @pgnames: array of pingroup names the function uses
85 * @npgnames: number of pingroup names the function uses
102 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @npins: number pins with the same mux value of gpio function
105 * @gpiofunc: mux value of gpio function
116 * struct pcs_data - wrapper for data needed by pinctrl framework
130 * struct pcs_soc_data - SoC specific settings
133 * @irq_enable_mask: optional SoC specific interrupt enable mask
134 * @irq_status_mask: optional SoC specific interrupt status mask
135 * @rearm: optional SoC specific wake-up rearm function
146 * struct pcs_device - pinctrl device instance
154 * @flags: mask of PCS_FEAT_xxx values
160 * @fmask: function register mask
161 * @fshift: function register shift
172 * @read: register read function to use
173 * @write: register write function to use
209 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
210 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
211 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
275 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
277 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
280 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
290 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
305 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
307 if (pcs->bits_per_mux) in pcs_pin_dbg_show()
308 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); in pcs_pin_dbg_show()
310 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
321 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
343 struct function_desc *function; in pcs_get_function() local
347 setting = pdesc->mux_setting; in pcs_get_function()
349 return -ENOTSUPP; in pcs_get_function()
350 fselector = setting->func; in pcs_get_function()
351 function = pinmux_generic_get_function(pctldev, fselector); in pcs_get_function()
352 if (!function) in pcs_get_function()
353 return -EINVAL; in pcs_get_function()
354 *func = function->data; in pcs_get_function()
356 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
358 return -ENOTSUPP; in pcs_get_function()
367 struct function_desc *function; in pcs_set_mux() local
372 /* If function mask is null, needn't enable it. */ in pcs_set_mux()
373 if (!pcs->fmask) in pcs_set_mux()
375 function = pinmux_generic_get_function(pctldev, fselector); in pcs_set_mux()
376 if (!function) in pcs_set_mux()
377 return -EINVAL; in pcs_set_mux()
378 func = function->data; in pcs_set_mux()
380 return -EINVAL; in pcs_set_mux()
382 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
383 func->name, fselector); in pcs_set_mux()
385 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
388 unsigned val, mask; in pcs_set_mux() local
390 vals = &func->vals[i]; in pcs_set_mux()
391 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
392 val = pcs->read(vals->reg); in pcs_set_mux()
394 if (pcs->bits_per_mux) in pcs_set_mux()
395 mask = vals->mask; in pcs_set_mux()
397 mask = pcs->fmask; in pcs_set_mux()
399 val &= ~mask; in pcs_set_mux()
400 val |= (vals->val & mask); in pcs_set_mux()
401 pcs->write(val, vals->reg); in pcs_set_mux()
402 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
416 /* If function mask is null, return directly. */ in pcs_request_gpio()
417 if (!pcs->fmask) in pcs_request_gpio()
418 return -ENOTSUPP; in pcs_request_gpio()
420 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
424 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
425 || pin < frange->offset) in pcs_request_gpio()
430 if (pcs->bits_per_mux) { in pcs_request_gpio()
433 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
434 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
435 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
436 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
438 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
439 data &= ~pcs->fmask; in pcs_request_gpio()
440 data |= frange->gpiofunc; in pcs_request_gpio()
441 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
498 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
505 return -ENOTSUPP; in pcs_pinconf_get()
507 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
511 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
512 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
513 switch (func->conf[i].param) { in pcs_pinconf_get()
518 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
519 (data == func->conf[i].disable)) in pcs_pinconf_get()
520 return -ENOTSUPP; in pcs_pinconf_get()
525 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
526 switch (func->conf[j].param) { in pcs_pinconf_get()
528 if (data != func->conf[j].enable) in pcs_pinconf_get()
529 return -ENOTSUPP; in pcs_pinconf_get()
547 return -ENOTSUPP; in pcs_pinconf_get()
565 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
567 != func->conf[i].param) in pcs_pinconf_set()
570 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
571 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
573 switch (func->conf[i].param) { in pcs_pinconf_set()
580 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
581 data &= ~func->conf[i].mask; in pcs_pinconf_set()
582 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
594 data &= ~func->conf[i].mask; in pcs_pinconf_set()
596 data |= func->conf[i].enable; in pcs_pinconf_set()
598 data |= func->conf[i].disable; in pcs_pinconf_set()
601 return -ENOTSUPP; in pcs_pinconf_set()
603 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
607 if (i >= func->nconfs) in pcs_pinconf_set()
608 return -ENOTSUPP; in pcs_pinconf_set()
626 return -ENOTSUPP; in pcs_pinconf_group_get()
629 return -ENOTSUPP; in pcs_pinconf_group_get()
648 return -ENOTSUPP; in pcs_pinconf_group_set()
682 * pcs_add_pin() - add a pin to the static per controller pin array
688 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
692 i = pcs->pins.cur; in pcs_add_pin()
693 if (i >= pcs->desc.npins) { in pcs_add_pin()
694 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
695 pcs->desc.npins); in pcs_add_pin()
696 return -ENOMEM; in pcs_add_pin()
699 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
702 val = pcs->read(pcs->base + offset); in pcs_add_pin()
703 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
704 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
705 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
706 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
707 pcs->write(val, pcs->base + offset); in pcs_add_pin()
711 pin = &pcs->pins.pa[i]; in pcs_add_pin()
712 pin->number = i; in pcs_add_pin()
713 pcs->pins.cur++; in pcs_add_pin()
719 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
731 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
733 if (pcs->bits_per_mux && pcs->fmask) { in pcs_allocate_pin_table()
734 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
735 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
737 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
740 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
741 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
742 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
744 if (!pcs->pins.pa) in pcs_allocate_pin_table()
745 return -ENOMEM; in pcs_allocate_pin_table()
747 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
748 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
750 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
757 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
766 * pcs_add_function() - adds a new function to the function list
768 * @fcn: new function allocated
769 * @name: name of the function
770 * @vals: array of mux register value pairs used by the function
772 * @pgnames: array of pingroup names for the function
785 struct pcs_function *function; in pcs_add_function() local
788 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
789 if (!function) in pcs_add_function()
790 return -ENOMEM; in pcs_add_function()
792 function->vals = vals; in pcs_add_function()
793 function->nvals = nvals; in pcs_add_function()
794 function->name = name; in pcs_add_function()
796 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
798 function); in pcs_add_function()
800 devm_kfree(pcs->dev, function); in pcs_add_function()
803 *fcn = function; in pcs_add_function()
810 * pcs_get_pin_by_offset() - get a pin index based on the register offset
820 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
821 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
822 offset, pcs->size); in pcs_get_pin_by_offset()
823 return -EINVAL; in pcs_get_pin_by_offset()
826 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
827 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
829 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
841 int ret = -EINVAL; in pcs_config_match()
852 unsigned mask) in add_config() argument
854 (*conf)->param = param; in add_config()
855 (*conf)->val = value; in add_config()
856 (*conf)->enable = enable; in add_config()
857 (*conf)->disable = disable; in add_config()
858 (*conf)->mask = mask; in add_config()
880 /* set value & mask */ in pcs_add_conf2()
882 shift = ffs(value[1]) - 1; in pcs_add_conf2()
896 /* value to set, enable, disable, mask */ in pcs_add_conf4()
901 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
909 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
924 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
925 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
926 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, in pcs_parse_pinconf()
927 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
928 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, in pcs_parse_pinconf()
931 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
932 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
933 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
939 return -ENOTSUPP; in pcs_parse_pinconf()
951 return -ENOTSUPP; in pcs_parse_pinconf()
953 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
956 if (!func->conf) in pcs_parse_pinconf()
957 return -ENOMEM; in pcs_parse_pinconf()
958 func->nconfs = nconfs; in pcs_parse_pinconf()
959 conf = &(func->conf[0]); in pcs_parse_pinconf()
961 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
964 return -ENOMEM; in pcs_parse_pinconf()
973 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
974 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
975 m->data.configs.configs = settings; in pcs_parse_pinconf()
976 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
981 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
990 * Also note that this driver tries to avoid understanding pin and function
994 * decipher the pin and function names using debugfs.
1005 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
1007 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
1008 struct pcs_function *function = NULL; in pcs_parse_one_pinctrl_entry() local
1012 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
1013 return -EINVAL; in pcs_parse_one_pinctrl_entry()
1016 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1018 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1020 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1034 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1040 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1051 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1056 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1064 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1065 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1066 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1073 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1079 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1080 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1081 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1083 if (PCS_HAS_PINCONF && function) { in pcs_parse_one_pinctrl_entry()
1084 res = pcs_parse_pinconf(pcs, np, function, map); in pcs_parse_one_pinctrl_entry()
1087 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1094 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1099 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1102 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1104 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1105 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1108 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1119 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1121 int rows, *pins, found = 0, res = -ENOMEM, i, fsel; in pcs_parse_bits_in_pinctrl_entry()
1123 struct pcs_function *function = NULL; in pcs_parse_bits_in_pinctrl_entry() local
1127 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1128 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1132 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1133 return -ENOTSUPP; in pcs_parse_bits_in_pinctrl_entry()
1136 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1138 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1142 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1144 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1153 unsigned mask, bit_pos, val_pos, mask_pos, submask; in pcs_parse_bits_in_pinctrl_entry() local
1162 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1170 mask = pinctrl_spec.args[2]; in pcs_parse_bits_in_pinctrl_entry()
1172 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1173 pinctrl_spec.np, offset, val, mask); in pcs_parse_bits_in_pinctrl_entry()
1176 while (mask) { in pcs_parse_bits_in_pinctrl_entry()
1177 bit_pos = __ffs(mask); in pcs_parse_bits_in_pinctrl_entry()
1178 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1179 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1181 submask = mask & mask_pos; in pcs_parse_bits_in_pinctrl_entry()
1183 if ((mask & mask_pos) == 0) { in pcs_parse_bits_in_pinctrl_entry()
1184 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1185 "Invalid mask for %pOFn at 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1190 mask &= ~mask_pos; in pcs_parse_bits_in_pinctrl_entry()
1193 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1199 vals[found].mask = submask; in pcs_parse_bits_in_pinctrl_entry()
1200 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1205 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1214 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1215 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1216 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1223 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1227 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1228 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1229 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1232 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1237 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1239 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1240 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1243 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1248 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1265 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1267 return -ENOMEM; in pcs_dt_node_to_map()
1271 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1273 ret = -ENOMEM; in pcs_dt_node_to_map()
1277 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1281 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1289 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1298 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1300 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1306 * pcs_irq_free() - free interrupt
1311 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1313 if (pcs_soc->irq < 0) in pcs_irq_free()
1316 if (pcs->domain) in pcs_irq_free()
1317 irq_domain_remove(pcs->domain); in pcs_irq_free()
1320 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1322 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1326 * pcs_free_resources() - free memory used by this driver
1334 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1335 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1341 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1342 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1355 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1357 ret = -ENOMEM; in pcs_add_gpio_func()
1360 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1361 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1362 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1363 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1364 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1365 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1385 * pcs_irq_set() - enables or disables an interrupt
1391 * register that is typically used for wake-up events.
1398 unsigned mask; in pcs_irq_set() local
1401 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1406 if (irq != pcswi->irq) in pcs_irq_set()
1409 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1410 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1411 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1413 mask |= soc_mask; in pcs_irq_set()
1415 mask &= ~soc_mask; in pcs_irq_set()
1416 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1419 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1420 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1423 if (pcs_soc->rearm) in pcs_irq_set()
1424 pcs_soc->rearm(); in pcs_irq_set()
1428 * pcs_irq_mask() - mask pinctrl interrupt
1435 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1439 * pcs_irq_unmask() - unmask pinctrl interrupt
1446 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1450 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1452 * @state: wake-up state
1455 * For runtime PM, the wake-up events should be enabled by default.
1468 * pcs_irq_handle() - common interrupt handler
1472 * mux register. This interrupt is typically used for wake-up events.
1482 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1484 unsigned mask; in pcs_irq_handle() local
1487 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1488 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1489 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1490 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1491 generic_handle_domain_irq(pcs->domain, in pcs_irq_handle()
1492 pcswi->hwirq); in pcs_irq_handle()
1501 * pcs_irq_handler() - handler for the shared interrupt case
1506 * pinctrl-single share a single interrupt like on omaps.
1516 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1520 * pinctrl-single instance.
1537 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1542 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1544 return -ENOMEM; in pcs_irqdomain_map()
1546 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1547 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1548 pcswi->irq = irq; in pcs_irqdomain_map()
1550 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1551 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1552 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1555 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1569 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1576 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1580 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1581 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1582 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1583 return -EINVAL; in pcs_irq_init_chained_handler()
1586 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1587 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1588 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1589 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1590 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1591 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1596 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1601 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1605 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1614 * interrupt per function if needed. in pcs_irq_init_chained_handler()
1616 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1618 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1621 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1622 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1623 return -EINVAL; in pcs_irq_init_chained_handler()
1637 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1639 if (!pcs->saved_vals) { in pcs_save_context()
1640 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1641 if (!pcs->saved_vals) in pcs_save_context()
1642 return -ENOMEM; in pcs_save_context()
1645 switch (pcs->width) { in pcs_save_context()
1647 regsl = pcs->saved_vals; in pcs_save_context()
1648 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1649 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1652 regsw = pcs->saved_vals; in pcs_save_context()
1653 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1654 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1657 regshw = pcs->saved_vals; in pcs_save_context()
1658 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1659 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1673 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1675 switch (pcs->width) { in pcs_restore_context()
1677 regsl = pcs->saved_vals; in pcs_restore_context()
1678 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1679 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1682 regsw = pcs->saved_vals; in pcs_restore_context()
1683 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1684 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1687 regshw = pcs->saved_vals; in pcs_restore_context()
1688 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1689 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1701 return -EINVAL; in pinctrl_single_suspend()
1703 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend()
1711 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend()
1720 return -EINVAL; in pinctrl_single_resume()
1722 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume()
1725 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume()
1730 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1735 * Handle legacy binding with no #pinctrl-cells. This should be
1736 * always two pinctrl-single,bit-per-mux and one for others.
1744 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1752 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1755 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1757 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1759 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1760 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1761 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1762 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1763 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1765 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1766 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1767 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1769 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1772 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1780 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1787 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1789 return -EINVAL; in pcs_probe()
1791 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1793 return -ENOMEM; in pcs_probe()
1795 pcs->dev = &pdev->dev; in pcs_probe()
1796 pcs->np = np; in pcs_probe()
1797 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1798 mutex_init(&pcs->mutex); in pcs_probe()
1799 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1800 pcs->flags = soc->flags; in pcs_probe()
1801 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1803 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1804 &pcs->width); in pcs_probe()
1806 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1811 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1812 &pcs->fmask); in pcs_probe()
1814 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1815 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1817 /* If mask property doesn't exist, function mux is invalid. */ in pcs_probe()
1818 pcs->fmask = 0; in pcs_probe()
1819 pcs->fshift = 0; in pcs_probe()
1820 pcs->fmax = 0; in pcs_probe()
1823 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1824 &pcs->foff); in pcs_probe()
1826 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1828 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1829 "pinctrl-single,bit-per-mux"); in pcs_probe()
1831 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1833 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1840 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1841 return -ENODEV; in pcs_probe()
1844 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1846 if (!pcs->res) { in pcs_probe()
1847 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1848 return -EBUSY; in pcs_probe()
1851 pcs->size = resource_size(pcs->res); in pcs_probe()
1852 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1853 if (!pcs->base) { in pcs_probe()
1854 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1855 return -ENODEV; in pcs_probe()
1860 switch (pcs->width) { in pcs_probe()
1862 pcs->read = pcs_readb; in pcs_probe()
1863 pcs->write = pcs_writeb; in pcs_probe()
1866 pcs->read = pcs_readw; in pcs_probe()
1867 pcs->write = pcs_writew; in pcs_probe()
1870 pcs->read = pcs_readl; in pcs_probe()
1871 pcs->write = pcs_writel; in pcs_probe()
1877 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1878 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1879 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1881 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1882 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1888 ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl); in pcs_probe()
1890 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1898 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1899 if (pcs->socdata.irq) in pcs_probe()
1900 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1903 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1905 if (pdata->rearm) in pcs_probe()
1906 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1907 if (pdata->irq) { in pcs_probe()
1908 pcs->socdata.irq = pdata->irq; in pcs_probe()
1909 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1916 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1919 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1921 ret = pinctrl_enable(pcs->pctl); in pcs_probe()
1975 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1976 { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1977 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1978 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1979 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1980 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1981 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1982 { .compatible = "pinconf-single", .data = &pinconf_single },
2003 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");