Lines Matching +full:rk3568 +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
93 { .offset = -1 }, \
94 { .offset = -1 }, \
95 { .offset = -1 }, \
96 { .offset = -1 }, \
99 { .drv_type = type0, .offset = -1 }, \
100 { .drv_type = type1, .offset = -1 }, \
101 { .drv_type = type2, .offset = -1 }, \
102 { .drv_type = type3, .offset = -1 }, \
114 { .type = iom0, .offset = -1 }, \
115 { .type = iom1, .offset = -1 }, \
116 { .type = iom2, .offset = -1 }, \
117 { .type = iom3, .offset = -1 }, \
133 { .offset = -1 }, \
134 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
139 { .drv_type = drv0, .offset = -1 }, \
140 { .drv_type = drv1, .offset = -1 }, \
141 { .drv_type = drv2, .offset = -1 }, \
142 { .drv_type = drv3, .offset = -1 }, \
174 { .type = iom0, .offset = -1 }, \
175 { .type = iom1, .offset = -1 }, \
176 { .type = iom2, .offset = -1 }, \
177 { .type = iom3, .offset = -1 }, \
198 { .type = iom0, .offset = -1 }, \
199 { .type = iom1, .offset = -1 }, \
200 { .type = iom2, .offset = -1 }, \
201 { .type = iom3, .offset = -1 }, \
249 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
250 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
251 return &info->groups[i]; in pinctrl_name_to_group()
264 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
266 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
276 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
280 if (b->bank_num == num) in bank_num_to_bank()
284 return ERR_PTR(-EINVAL); in bank_num_to_bank()
295 return info->ngroups; in rockchip_get_groups_count()
303 return info->groups[selector].name; in rockchip_get_group_name()
312 if (selector >= info->ngroups) in rockchip_get_group_pins()
313 return -EINVAL; in rockchip_get_group_pins()
315 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
316 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
327 struct device *dev = info->dev; in rockchip_dt_node_to_map()
337 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
340 return -EINVAL; in rockchip_dt_node_to_map()
343 map_num += grp->npins; in rockchip_dt_node_to_map()
347 return -ENOMEM; in rockchip_dt_node_to_map()
356 return -EINVAL; in rockchip_dt_node_to_map()
359 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
360 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
365 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
368 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
369 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
370 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
374 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
705 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
706 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
710 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
711 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
712 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
713 data->pin == pin) in rockchip_get_recalced_mux()
717 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
720 *reg = data->reg; in rockchip_get_recalced_mux()
721 *mask = data->mask; in rockchip_get_recalced_mux()
722 *bit = data->bit; in rockchip_get_recalced_mux()
726 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
727 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
728 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
729 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
730 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
731 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
732 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
733 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
734 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
735 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
736 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
737 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
738 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
739 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
740 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
741 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
742 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
743 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
744 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
745 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
746 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
747 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
748 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
749 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
750 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
751 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
752 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
753 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
754 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
755 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
756 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
757 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
758 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
759 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
760 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
761 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
762 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
763 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
764 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
765 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
766 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
767 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
768 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
769 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
770 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
771 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
772 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
773 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
874 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
875 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
876 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
877 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
878 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
879 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
880 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
884 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
885 …UTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
889 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
890 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
891 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
892 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
893 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
894 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
895 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
896 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
897 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
898 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
899 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
900 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
901 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
902 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
903 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
904 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
905 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
906 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
920 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
921 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
922 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
923 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
924 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
925 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
926 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
927 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
933 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
934 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1052 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1053 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1057 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1058 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1059 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1060 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1064 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1067 *loc = data->route_location; in rockchip_get_mux_route()
1068 *reg = data->route_offset; in rockchip_get_mux_route()
1069 *value = data->route_val; in rockchip_get_mux_route()
1076 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1077 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux()
1085 return -EINVAL; in rockchip_get_mux()
1087 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1088 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1089 return -EINVAL; in rockchip_get_mux()
1092 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1095 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1096 regmap = info->regmap_pmu; in rockchip_get_mux()
1097 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_get_mux()
1098 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1100 regmap = info->regmap_base; in rockchip_get_mux()
1103 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1104 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1120 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1123 if (ctrl->type == RK3588) { in rockchip_get_mux()
1124 if (bank->bank_num == 0) { in rockchip_get_mux()
1128 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1137 regmap = info->regmap_base; in rockchip_get_mux()
1139 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1154 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1155 struct device *dev = info->dev; in rockchip_verify_mux()
1159 return -EINVAL; in rockchip_verify_mux()
1161 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1163 return -EINVAL; in rockchip_verify_mux()
1166 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1169 return -ENOTSUPP; in rockchip_verify_mux()
1191 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1192 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_mux()
1193 struct device *dev = info->dev; in rockchip_set_mux()
1204 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1207 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rockchip_set_mux()
1209 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1210 regmap = info->regmap_pmu; in rockchip_set_mux()
1211 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_set_mux()
1212 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1214 regmap = info->regmap_base; in rockchip_set_mux()
1217 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1218 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1234 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1237 if (ctrl->type == RK3588) { in rockchip_set_mux()
1238 if (bank->bank_num == 0) { in rockchip_set_mux()
1241 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1249 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1259 regmap = info->regmap_base; in rockchip_set_mux()
1269 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1275 return -EINVAL; in rockchip_set_mux()
1277 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1285 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1288 route_regmap = info->regmap_base; in rockchip_set_mux()
1316 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1318 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_pull_reg_and_bit()
1319 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1320 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1323 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1327 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1328 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1348 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1350 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_drv_reg_and_bit()
1351 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1352 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1355 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1359 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1360 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1381 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1384 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1385 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1389 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1392 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1411 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1413 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_pull_reg_and_bit()
1414 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1415 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1419 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1421 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1422 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1442 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1444 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_drv_reg_and_bit()
1445 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1446 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1449 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1453 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1454 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1475 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1478 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1479 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1483 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1486 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1505 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_pull_reg_and_bit()
1507 /* The first 24 pins of the first bank are located in PMU */ in rv1126_calc_pull_reg_and_bit()
1508 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1510 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1512 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); in rv1126_calc_pull_reg_and_bit()
1517 *regmap = info->regmap_pmu; in rv1126_calc_pull_reg_and_bit()
1521 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1522 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; in rv1126_calc_pull_reg_and_bit()
1542 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_drv_reg_and_bit()
1544 /* The first 24 pins of the first bank are located in PMU */ in rv1126_calc_drv_reg_and_bit()
1545 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1547 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1549 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); in rv1126_calc_drv_reg_and_bit()
1550 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1555 *regmap = info->regmap_pmu; in rv1126_calc_drv_reg_and_bit()
1558 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1560 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; in rv1126_calc_drv_reg_and_bit()
1581 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_schmitt_reg_and_bit()
1584 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1586 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1588 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); in rv1126_calc_schmitt_reg_and_bit()
1592 *regmap = info->regmap_pmu; in rv1126_calc_schmitt_reg_and_bit()
1596 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1599 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; in rv1126_calc_schmitt_reg_and_bit()
1615 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1617 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1620 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1635 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1637 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1653 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1655 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1657 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1675 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1678 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1679 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1680 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1681 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1686 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1687 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1688 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1691 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1692 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1700 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1712 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1714 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_pull_reg_and_bit()
1715 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1716 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1723 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1727 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1728 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1748 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1750 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_drv_reg_and_bit()
1751 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1752 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1759 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1763 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1764 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1780 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1782 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1784 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1799 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1801 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1803 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1818 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1820 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1822 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1837 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1839 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1841 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1857 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1859 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_pull_reg_and_bit()
1860 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1861 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1868 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1872 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1873 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1890 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1892 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_drv_reg_and_bit()
1893 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1894 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1901 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
1905 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1906 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
1924 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
1926 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_pull_reg_and_bit()
1927 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1928 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
1931 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1937 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
1941 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1942 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1956 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
1959 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_drv_reg_and_bit()
1960 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1961 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
1963 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
1965 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
1966 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
1967 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
1985 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
1987 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
1988 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
1990 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1996 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
1998 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
2018 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
2020 /* The first 32 pins of the first bank are located in PMU */ in rk3568_calc_drv_reg_and_bit()
2021 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
2022 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
2029 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
2031 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
2153 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_pull_reg_and_bit()
2154 u8 bank_num = bank->bank_num; in rk3588_calc_pull_reg_and_bit()
2158 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2161 *regmap = info->regmap_base; in rk3588_calc_pull_reg_and_bit()
2168 return -EINVAL; in rk3588_calc_pull_reg_and_bit()
2178 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_drv_reg_and_bit()
2179 u8 bank_num = bank->bank_num; in rk3588_calc_drv_reg_and_bit()
2183 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2186 *regmap = info->regmap_base; in rk3588_calc_drv_reg_and_bit()
2193 return -EINVAL; in rk3588_calc_drv_reg_and_bit()
2204 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_schmitt_reg_and_bit()
2205 u8 bank_num = bank->bank_num; in rk3588_calc_schmitt_reg_and_bit()
2209 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2212 *regmap = info->regmap_base; in rk3588_calc_schmitt_reg_and_bit()
2219 return -EINVAL; in rk3588_calc_schmitt_reg_and_bit()
2223 { 2, 4, 8, 12, -1, -1, -1, -1 },
2224 { 3, 6, 9, 12, -1, -1, -1, -1 },
2225 { 5, 10, 15, 20, -1, -1, -1, -1 },
2233 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2234 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
2235 struct device *dev = info->dev; in rockchip_get_drive_perpin()
2240 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2242 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2256 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
2280 bit -= 16; in rockchip_get_drive_perpin()
2285 return -EINVAL; in rockchip_get_drive_perpin()
2296 return -EINVAL; in rockchip_get_drive_perpin()
2304 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
2312 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2313 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
2314 struct device *dev = info->dev; in rockchip_set_drive_perpin()
2319 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2321 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
2322 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2324 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2327 if (ctrl->type == RK3588) { in rockchip_set_drive_perpin()
2331 } else if (ctrl->type == RK3568) { in rockchip_set_drive_perpin()
2333 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
2337 if (ctrl->type == RV1126) { in rockchip_set_drive_perpin()
2343 ret = -EINVAL; in rockchip_set_drive_perpin()
2369 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2391 bit -= 16; in rockchip_set_drive_perpin()
2396 return -EINVAL; in rockchip_set_drive_perpin()
2406 return -EINVAL; in rockchip_set_drive_perpin()
2411 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2437 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2438 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
2439 struct device *dev = info->dev; in rockchip_get_pull()
2446 if (ctrl->type == RK3066B) in rockchip_get_pull()
2449 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2457 switch (ctrl->type) { in rockchip_get_pull()
2471 case RK3568: in rockchip_get_pull()
2473 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2475 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2477 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_get_pull()
2480 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2488 return -EINVAL; in rockchip_get_pull()
2495 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2496 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
2497 struct device *dev = info->dev; in rockchip_set_pull()
2503 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); in rockchip_set_pull()
2506 if (ctrl->type == RK3066B) in rockchip_set_pull()
2507 return pull ? -EINVAL : 0; in rockchip_set_pull()
2509 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2513 switch (ctrl->type) { in rockchip_set_pull()
2530 case RK3568: in rockchip_set_pull()
2532 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2533 ret = -EINVAL; in rockchip_set_pull()
2542 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_set_pull()
2545 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2556 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2564 return -EINVAL; in rockchip_set_pull()
2580 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2582 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2585 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2603 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
2605 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2606 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
2609 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
2611 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
2623 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2624 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
2630 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2639 switch (ctrl->type) { in rockchip_get_schmitt()
2640 case RK3568: in rockchip_get_schmitt()
2641 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
2652 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2653 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
2654 struct device *dev = info->dev; in rockchip_set_schmitt()
2660 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2661 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2663 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2668 switch (ctrl->type) { in rockchip_set_schmitt()
2669 case RK3568: in rockchip_set_schmitt()
2670 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
2691 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2699 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2708 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2709 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2718 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2719 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2720 struct device *dev = info->dev; in rockchip_pmx_set()
2725 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2731 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2733 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2741 for (cnt--; cnt >= 0; cnt--) { in rockchip_pmx_set()
2743 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2761 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); in rockchip_pmx_gpio_set_direction()
2779 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2795 case RK3568: in rockchip_pinconf_pull_valid()
2810 return -ENOMEM; in rockchip_pinconf_defer_pin()
2812 cfg->pin = pin; in rockchip_pinconf_defer_pin()
2813 cfg->param = param; in rockchip_pinconf_defer_pin()
2814 cfg->arg = arg; in rockchip_pinconf_defer_pin()
2816 list_add_tail(&cfg->head, &bank->deferred_pins); in rockchip_pinconf_defer_pin()
2827 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_set()
2840 * The lock makes sure that either gpio-probe has completed in rockchip_pinconf_set()
2843 mutex_lock(&bank->deferred_lock); in rockchip_pinconf_set()
2844 if (!gpio || !gpio->direction_output) { in rockchip_pinconf_set()
2845 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, in rockchip_pinconf_set()
2847 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2853 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2858 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2867 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2868 return -ENOTSUPP; in rockchip_pinconf_set()
2871 return -EINVAL; in rockchip_pinconf_set()
2873 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2879 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2882 return -EINVAL; in rockchip_pinconf_set()
2884 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
2890 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2893 return -EINVAL; in rockchip_pinconf_set()
2895 rc = gpio->direction_input(gpio, pin - bank->pin_base); in rockchip_pinconf_set()
2900 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2901 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2902 return -ENOTSUPP; in rockchip_pinconf_set()
2905 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2910 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2911 return -ENOTSUPP; in rockchip_pinconf_set()
2914 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2919 return -ENOTSUPP; in rockchip_pinconf_set()
2933 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_get()
2940 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2941 return -EINVAL; in rockchip_pinconf_get()
2949 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2950 return -ENOTSUPP; in rockchip_pinconf_get()
2952 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2953 return -EINVAL; in rockchip_pinconf_get()
2958 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2960 return -EINVAL; in rockchip_pinconf_get()
2962 if (!gpio || !gpio->get) { in rockchip_pinconf_get()
2967 rc = gpio->get(gpio, pin - bank->pin_base); in rockchip_pinconf_get()
2974 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2975 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2976 return -ENOTSUPP; in rockchip_pinconf_get()
2978 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2985 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2986 return -ENOTSUPP; in rockchip_pinconf_get()
2988 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2995 return -ENOTSUPP; in rockchip_pinconf_get()
3011 { .compatible = "rockchip,gpio-bank" },
3012 { .compatible = "rockchip,rk3188-gpio-bank0" },
3025 info->nfunctions++; in rockchip_pinctrl_child_count()
3026 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
3035 struct device *dev = info->dev; in rockchip_pinctrl_parse_groups()
3046 grp->name = np->name; in rockchip_pinctrl_parse_groups()
3056 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
3058 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
3060 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3061 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3062 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
3063 return -ENOMEM; in rockchip_pinctrl_parse_groups()
3074 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3075 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3079 return -EINVAL; in rockchip_pinctrl_parse_groups()
3083 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
3096 struct device *dev = info->dev; in rockchip_pinctrl_parse_functions()
3106 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
3109 func->name = np->name; in rockchip_pinctrl_parse_functions()
3110 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
3111 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3114 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
3115 if (!func->groups) in rockchip_pinctrl_parse_functions()
3116 return -ENOMEM; in rockchip_pinctrl_parse_functions()
3119 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
3120 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
3134 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
3135 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
3142 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
3143 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
3145 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3146 if (!info->functions) in rockchip_pinctrl_parse_dt()
3147 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3149 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3150 if (!info->groups) in rockchip_pinctrl_parse_dt()
3151 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3173 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
3176 struct device *dev = &pdev->dev; in rockchip_pinctrl_register()
3181 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
3182 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
3183 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
3184 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
3185 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
3187 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); in rockchip_pinctrl_register()
3189 return -ENOMEM; in rockchip_pinctrl_register()
3191 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
3192 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
3195 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3196 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3198 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); in rockchip_pinctrl_register()
3202 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3203 pdesc->number = k; in rockchip_pinctrl_register()
3204 pdesc->name = pin_names[pin]; in rockchip_pinctrl_register()
3208 INIT_LIST_HEAD(&pin_bank->deferred_pins); in rockchip_pinctrl_register()
3209 mutex_init(&pin_bank->deferred_lock); in rockchip_pinctrl_register()
3216 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); in rockchip_pinctrl_register()
3217 if (IS_ERR(info->pctl_dev)) in rockchip_pinctrl_register()
3218 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
3230 struct device *dev = &pdev->dev; in rockchip_pinctrl_get_soc_data()
3231 struct device_node *node = dev->of_node; in rockchip_pinctrl_get_soc_data()
3238 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3240 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3241 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3242 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3243 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3244 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3245 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3248 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3249 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3250 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3251 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3255 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3256 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3259 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3263 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3264 if ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3265 (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3266 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3268 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3270 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3271 (iom->type & IOMUX_L_SOURCE_PMU)) ? in rockchip_pinctrl_get_soc_data()
3276 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3277 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3278 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3280 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3282 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3287 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3293 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3296 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3303 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3305 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3306 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3311 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3319 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3320 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3323 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3324 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3325 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3329 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3330 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3333 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3334 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3335 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3351 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3360 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3361 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3364 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3377 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
3378 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3385 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3394 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3395 struct device_node *np = dev->of_node, *node; in rockchip_pinctrl_probe()
3401 if (!dev->of_node) in rockchip_pinctrl_probe()
3402 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); in rockchip_pinctrl_probe()
3406 return -ENOMEM; in rockchip_pinctrl_probe()
3408 info->dev = dev; in rockchip_pinctrl_probe()
3412 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); in rockchip_pinctrl_probe()
3413 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3417 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3419 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3420 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3426 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3428 info->regmap_base = in rockchip_pinctrl_probe()
3431 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3432 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3435 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3440 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3441 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3442 info->regmap_pull = in rockchip_pinctrl_probe()
3447 /* try to find the optional reference to the pmu syscon */ in rockchip_pinctrl_probe()
3448 node = of_parse_phandle(np, "rockchip,pmu", 0); in rockchip_pinctrl_probe()
3450 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3452 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3453 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3462 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); in rockchip_pinctrl_probe()
3476 of_platform_depopulate(&pdev->dev); in rockchip_pinctrl_remove()
3478 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
3479 bank = &info->ctrl->pin_banks[i]; in rockchip_pinctrl_remove()
3481 mutex_lock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3482 while (!list_empty(&bank->deferred_pins)) { in rockchip_pinctrl_remove()
3483 cfg = list_first_entry(&bank->deferred_pins, in rockchip_pinctrl_remove()
3485 list_del(&cfg->head); in rockchip_pinctrl_remove()
3488 mutex_unlock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3520 .label = "PX30-GPIO",
3544 .label = "RV1108-GPIO",
3584 .label = "RV1126-GPIO",
3607 .label = "RK2928-GPIO",
3622 .label = "RK3036-GPIO",
3640 .label = "RK3066a-GPIO",
3656 .label = "RK3066b-GPIO",
3671 .label = "RK3128-GPIO",
3691 .label = "RK3188-GPIO",
3709 .label = "RK3228-GPIO",
3753 .label = "RK3288-GPIO",
3789 .label = "RK3308-GPIO",
3818 .label = "RK3328-GPIO",
3844 .label = "RK3368-GPIO",
3864 -1,
3865 -1,
3908 .label = "RK3399-GPIO",
3946 .label = "RK3568-GPIO",
3947 .type = RK3568,
3975 .label = "RK3588-GPIO",
3983 { .compatible = "rockchip,px30-pinctrl",
3985 { .compatible = "rockchip,rv1108-pinctrl",
3987 { .compatible = "rockchip,rv1126-pinctrl",
3989 { .compatible = "rockchip,rk2928-pinctrl",
3991 { .compatible = "rockchip,rk3036-pinctrl",
3993 { .compatible = "rockchip,rk3066a-pinctrl",
3995 { .compatible = "rockchip,rk3066b-pinctrl",
3997 { .compatible = "rockchip,rk3128-pinctrl",
3999 { .compatible = "rockchip,rk3188-pinctrl",
4001 { .compatible = "rockchip,rk3228-pinctrl",
4003 { .compatible = "rockchip,rk3288-pinctrl",
4005 { .compatible = "rockchip,rk3308-pinctrl",
4007 { .compatible = "rockchip,rk3328-pinctrl",
4009 { .compatible = "rockchip,rk3368-pinctrl",
4011 { .compatible = "rockchip,rk3399-pinctrl",
4013 { .compatible = "rockchip,rk3568-pinctrl",
4015 { .compatible = "rockchip,rk3588-pinctrl",
4024 .name = "rockchip-pinctrl",
4044 MODULE_ALIAS("platform:pinctrl-rockchip");