Lines Matching refs:pctl_readl
832 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg) in pctl_readl() function
965 val = pctl_readl(pctl, pg->mux_reg); in pistachio_pinmux_enable()
978 val = pctl_readl(pctl, pf->scenario_reg); in pistachio_pinmux_enable()
1008 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); in pistachio_pinconf_get()
1012 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1017 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1022 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1027 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1032 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); in pistachio_pinconf_get()
1036 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> in pistachio_pinconf_get()
1078 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); in pistachio_pinconf_set()
1086 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1092 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1098 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1104 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1110 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); in pistachio_pinconf_set()
1118 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); in pistachio_pinconf_set()