Lines Matching +full:txrx +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
164 (!(enabled_socs & GENMASK(version - 1, 0)) in is_soc_or_above()
165 || jzpc->info->version >= version); in is_soc_or_above()
203 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
204 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
205 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
206 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
207 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
208 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
209 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
210 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
211 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
212 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
213 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
214 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
215 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
216 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
217 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
218 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
223 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
224 static const char *jz4730_uart0_groups[] = { "uart0-data", };
225 static const char *jz4730_uart1_groups[] = { "uart1-data", };
226 static const char *jz4730_uart2_groups[] = { "uart2-data", };
227 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
229 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
232 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
299 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
300 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
301 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
302 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
303 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
304 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
305 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
306 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
307 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
308 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
309 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
310 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
311 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
312 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
313 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
324 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
325 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
326 static const char *jz4740_uart1_groups[] = { "uart1-data", };
328 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
331 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
402 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
403 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
405 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
406 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
407 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
408 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
409 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
410 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
411 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
412 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
413 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
414 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
415 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
416 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
417 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
418 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
419 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
428 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
429 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
430 static const char *jz4725b_uart_groups[] = { "uart-data", };
432 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
433 "lcd-special", "lcd-generic",
436 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
437 "nand-cle-ale", "nand-fre-fwe",
521 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
522 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
523 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
524 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
525 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
526 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
527 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
528 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
529 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
530 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
531 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
532 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
533 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
534 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
535 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
536 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
537 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
538 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
539 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
540 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
541 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
542 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
543 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
544 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
545 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
554 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
555 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
556 static const char *jz4750_uart2_groups[] = { "uart2-data", };
557 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
559 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
561 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
562 static const char *jz4750_i2c_groups[] = { "i2c-data", };
563 static const char *jz4750_cim_groups[] = { "cim-data", };
565 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
566 "lcd-special", "lcd-generic",
569 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
670 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
671 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
672 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
673 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
674 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
675 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
676 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
677 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
678 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
679 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
680 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
681 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
682 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
683 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
684 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
685 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
686 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
688 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
690 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
691 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
692 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
693 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
694 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
695 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
696 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
697 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
699 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
700 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
701 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
702 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
703 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
704 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
705 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
714 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
715 static const char *jz4755_uart1_groups[] = { "uart1-data", };
716 static const char *jz4755_uart2_groups[] = { "uart2-data", };
718 "ssi-dt-b", "ssi-dt-f",
719 "ssi-dr-b", "ssi-dr-f",
720 "ssi-clk-b", "ssi-clk-f",
721 "ssi-gpc-b", "ssi-gpc-f",
722 "ssi-ce0-b", "ssi-ce0-f",
723 "ssi-ce1-b", "ssi-ce1-f",
725 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
726 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
727 static const char *jz4755_i2c_groups[] = { "i2c-data", };
728 static const char *jz4755_cim_groups[] = { "cim-data", };
730 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
731 "lcd-special", "lcd-generic",
734 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
909 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
910 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
911 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
912 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
913 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
914 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
915 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
917 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
918 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
919 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
920 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
921 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
922 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
923 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
924 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
925 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
926 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
927 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
928 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
929 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
930 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
931 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
932 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
933 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
934 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
935 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
936 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
937 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
938 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
939 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
940 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
941 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
942 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
943 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
944 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
945 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
946 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
947 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
948 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
949 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
950 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
951 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
952 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
953 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
954 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
955 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
956 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
957 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
958 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
959 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
960 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
961 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
962 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
963 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
964 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
965 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
966 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
967 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
968 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
969 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
970 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
972 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
973 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
974 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
975 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
976 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
977 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
978 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
979 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
980 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
981 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
982 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
983 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
984 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
985 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
986 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
987 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
988 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
989 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
990 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
991 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
992 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
993 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
994 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
995 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
996 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
997 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
998 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
999 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1000 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1001 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1002 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1003 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1004 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1005 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1006 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1007 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1016 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1019 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1020 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1021 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1022 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1024 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1025 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1026 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1027 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1028 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1029 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1032 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1033 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1034 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1035 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1036 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1037 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1040 "mmc0-1bit-a", "mmc0-4bit-a",
1041 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1044 "mmc1-1bit-d", "mmc1-4bit-d",
1045 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1048 "mmc2-1bit-b", "mmc2-4bit-b",
1049 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1052 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1053 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1055 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1056 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1057 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1058 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1059 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1060 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1061 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1062 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1063 static const char *jz4760_cim_groups[] = { "cim-data", };
1065 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1066 "lcd-special", "lcd-generic",
1076 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1089 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1090 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1091 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1092 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1093 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1094 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1254 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1255 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1256 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1257 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1258 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1259 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1260 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1262 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1263 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1264 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1265 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1266 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1267 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1268 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1269 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1270 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1271 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1272 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1273 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1274 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1275 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1276 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1277 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1278 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1279 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1280 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1281 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1282 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1283 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1284 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1285 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1286 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1287 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1288 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1289 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1290 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1291 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1292 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1293 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1294 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1295 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1296 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1297 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1298 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1299 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1300 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1301 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1302 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1303 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1305 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1306 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1307 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1308 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1309 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1310 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1311 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1312 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1313 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1314 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1315 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1316 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1317 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1318 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1319 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1320 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1321 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1322 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1323 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1324 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1325 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1326 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1327 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1328 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1329 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1330 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1331 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1332 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1333 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1334 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1335 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1336 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1337 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1338 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1339 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1340 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1341 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1342 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1351 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1352 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1353 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1356 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1357 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1358 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1359 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1361 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1362 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1363 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1364 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1365 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1366 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1369 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1370 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1371 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1372 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1373 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1374 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1377 "mmc0-1bit-a", "mmc0-4bit-a",
1378 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1381 "mmc1-1bit-d", "mmc1-4bit-d",
1382 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1385 "mmc2-1bit-b", "mmc2-4bit-b",
1386 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1389 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1390 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1392 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1393 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1394 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1395 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1396 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1397 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1398 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1399 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1400 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1401 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1403 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1404 "lcd-special", "lcd-generic",
1414 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1427 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1428 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1429 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1430 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1431 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1432 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1573 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1574 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1575 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1576 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1577 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1578 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1579 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1581 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1582 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1583 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1584 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1585 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1586 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1587 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1588 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1589 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1590 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1591 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1592 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1593 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1594 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1595 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1596 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1597 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1598 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1599 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1600 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1601 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1602 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1603 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1604 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1605 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1606 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1607 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1608 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1609 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1610 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1611 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1612 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1613 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1614 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1615 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1616 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1617 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1618 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1619 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1620 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1622 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1623 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1624 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1625 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1626 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1627 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1628 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1633 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1634 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1636 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1638 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1640 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1643 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1644 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1645 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1646 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1648 "ssi-dt-a", "ssi-dt-d",
1649 "ssi-dr-a", "ssi-dr-d",
1650 "ssi-clk-a", "ssi-clk-d",
1651 "ssi-gpc",
1652 "ssi-ce0-a", "ssi-ce0-d",
1653 "ssi-ce1",
1656 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1657 "mmc0-1bit-e", "mmc0-4bit-e",
1660 "mmc1-1bit-d", "mmc1-4bit-d",
1661 "mmc1-1bit-e", "mmc1-4bit-e",
1664 "mmc2-1bit-b", "mmc2-4bit-b",
1665 "mmc2-1bit-e", "mmc2-4bit-e",
1668 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1669 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1671 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1672 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1673 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1674 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1675 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1676 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1678 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1681 static const char *jz4775_cim_groups[] = { "cim-data", };
1683 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1684 "lcd-special", "lcd-generic",
1691 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1693 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1705 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1706 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1707 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1794 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1795 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1796 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1797 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1798 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1799 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1800 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1802 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1803 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1804 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1805 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1806 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1807 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1808 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1809 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1810 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1811 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1812 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1813 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1814 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1815 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1816 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1817 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1818 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1819 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1820 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1821 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1822 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1823 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1824 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1825 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1826 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1827 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1828 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1829 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1830 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1831 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1832 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1833 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1834 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1835 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1836 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1837 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1838 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1839 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1840 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1841 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1842 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1843 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1844 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1845 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1846 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1847 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1848 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1849 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1851 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1852 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1853 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1854 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1855 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1856 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1857 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1858 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1859 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1860 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1861 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1862 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1863 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1864 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1865 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1866 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1867 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1868 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1869 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1870 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1871 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1872 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1873 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1874 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1875 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1876 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1877 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1878 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1879 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1880 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1881 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1882 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1883 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1885 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1886 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1888 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1889 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1890 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1891 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1892 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1893 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1894 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1895 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1896 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1907 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1908 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1910 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1911 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1912 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1913 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1914 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1915 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1918 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1919 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1920 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1921 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1922 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1923 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1926 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1927 "mmc0-1bit-e", "mmc0-4bit-e",
1930 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1933 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1936 "nemc-data", "nemc-cle-ale", "nemc-addr",
1937 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1939 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1940 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1942 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1945 static const char *jz4780_cim_groups[] = { "cim-data", };
1946 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1960 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1961 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1962 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1963 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1964 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1965 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1983 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
2083 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2084 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2085 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2086 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2087 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2088 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2089 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2090 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2091 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2092 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2093 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2094 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2095 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2096 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2097 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2098 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2099 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2100 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2101 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2102 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2103 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2104 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2105 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2106 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2107 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2108 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2109 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2110 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2111 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2112 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2113 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2114 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2115 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2116 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2117 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2118 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2119 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2120 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2121 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2122 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2123 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2124 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2125 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2126 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2127 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2128 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2129 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2130 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2131 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2132 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2133 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2142 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2144 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2146 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2147 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2149 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2150 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2151 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2152 "ssi-gpc-a-20", "ssi-gpc-a-31",
2153 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2154 "ssi-ce1-a-21", "ssi-ce1-a-30",
2157 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2160 "mmc1-1bit", "mmc1-4bit",
2163 "emc-8bit-data", "emc-16bit-data",
2164 "emc-addr", "emc-rd-we", "emc-wait",
2166 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2167 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2168 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2169 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2170 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2172 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2174 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2175 static const char *x1000_cim_groups[] = { "cim-data", };
2176 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2193 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2194 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
2211 regmap_reg_range(0x000, 0x400 - 4),
2212 regmap_reg_range(0x700, 0x800 - 4),
2264 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2265 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2266 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2267 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2268 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2269 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2270 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2271 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2272 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2273 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2274 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2275 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2276 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2277 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2278 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2279 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2280 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2281 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2282 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2283 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2284 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2285 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2286 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2294 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2296 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2298 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2299 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2300 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2301 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2302 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2304 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2306 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2307 static const char *x1500_cim_groups[] = { "cim-data", };
2428 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2429 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2430 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2431 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2432 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2433 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2434 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2435 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2436 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2437 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2438 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2439 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2440 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2441 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2442 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2443 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2444 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2445 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2446 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2447 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2448 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2449 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2450 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2451 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2452 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2453 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2454 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2455 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2456 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2457 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2458 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2459 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2460 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2461 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2462 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2463 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2464 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2465 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2466 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2467 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2468 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2469 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2470 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2471 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2472 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2473 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2474 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2475 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2476 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2477 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2478 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2479 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2480 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2481 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2482 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2483 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2484 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2485 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2489 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2490 static const char *x1830_uart1_groups[] = { "uart1-data", };
2491 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2493 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2496 "ssi1-dt-c", "ssi1-dt-d",
2497 "ssi1-dr-c", "ssi1-dr-d",
2498 "ssi1-clk-c", "ssi1-clk-d",
2499 "ssi1-gpc-c", "ssi1-gpc-d",
2500 "ssi1-ce0-c", "ssi1-ce0-d",
2501 "ssi1-ce1-c", "ssi1-ce1-d",
2503 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2504 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2505 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2506 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2507 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2509 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2511 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2513 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2515 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2516 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2517 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2518 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2519 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2520 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2521 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2522 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2551 regmap_reg_range(0x0000, 0x4000 - 4),
2552 regmap_reg_range(0x7000, 0x8000 - 4),
2749 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2750 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2751 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2752 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2753 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2754 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2755 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2756 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2757 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2758 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2759 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2760 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2761 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2762 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2763 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2764 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2765 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2766 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2767 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2768 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2769 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2770 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2771 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2772 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2773 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2774 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2775 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2776 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2777 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2778 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2779 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2780 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2781 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2782 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2783 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2784 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2785 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2786 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2787 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2788 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2789 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2790 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2791 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2792 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2793 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2794 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2795 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2796 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2797 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2798 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2799 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2800 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2801 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2802 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2803 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2804 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2805 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2806 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2807 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2808 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2809 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2810 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2811 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2812 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2813 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2814 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2815 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2816 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2817 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2818 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2819 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2820 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2821 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2822 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2823 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2824 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2825 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2826 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2827 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2828 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2829 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2830 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2831 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2832 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2833 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2834 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2835 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2836 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2837 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2838 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2839 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2840 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2841 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2842 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2843 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2844 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2845 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2847 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2848 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2849 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2850 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2851 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2852 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2853 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2854 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2855 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2856 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2857 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2858 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2859 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2860 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2861 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2862 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2863 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2864 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2865 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2866 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2867 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2868 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2869 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2878 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2879 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2880 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2881 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2882 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2885 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2886 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2887 static const char *x2000_uart2_groups[] = { "uart2-data", };
2889 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2892 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2894 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2895 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2896 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2897 static const char *x2000_uart8_groups[] = { "uart8-data", };
2898 static const char *x2000_uart9_groups[] = { "uart9-data", };
2900 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2901 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2904 "ssi0-dt-b", "ssi0-dt-d",
2905 "ssi0-dr-b", "ssi0-dr-d",
2906 "ssi0-clk-b", "ssi0-clk-d",
2907 "ssi0-ce-b", "ssi0-ce-d",
2910 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2911 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2912 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2913 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2915 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2916 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2917 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2919 "emc-8bit-data", "emc-16bit-data",
2920 "emc-addr", "emc-rd-we", "emc-wait",
2922 static const char *x2000_cs1_groups[] = { "emc-cs1", };
2923 static const char *x2000_cs2_groups[] = { "emc-cs2", };
2924 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2925 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2926 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2927 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2928 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2929 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2931 "i2s1-data-tx", "i2s1-data-rx",
2932 "i2s1-clk-tx", "i2s1-clk-rx",
2933 "i2s1-sysclk-tx", "i2s1-sysclk-rx",
2936 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2937 "i2s2-clk-rx", "i2s2-sysclk-rx",
2940 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2941 "i2s3-clk-tx", "i2s3-sysclk-tx",
2944 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2946 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2948 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2949 "lcd-slcd-8bit", "lcd-slcd-16bit",
2951 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2952 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2953 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2954 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2955 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2956 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2957 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2958 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2967 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2968 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2969 static const char *x2000_otg_groups[] = { "otg-vbus", };
2989 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2990 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3025 regmap_reg_range(0x000, 0x500 - 4),
3026 regmap_reg_range(0x700, 0x800 - 4),
3061 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3062 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3063 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3064 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3065 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3066 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3067 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3068 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3069 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3070 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3071 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3072 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3073 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3074 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3075 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3076 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3077 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3078 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3079 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3080 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3081 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3082 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3083 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3084 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3085 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3086 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3087 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3088 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3089 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3090 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3091 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3092 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3093 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3094 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3095 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3096 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3097 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3098 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3099 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3100 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3101 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3102 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3103 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3104 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3105 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3106 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3107 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3108 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3109 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3110 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3111 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3112 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3113 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3114 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3115 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3116 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3117 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3118 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3119 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3120 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3121 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3122 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3123 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3124 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3125 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3126 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3127 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3128 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3129 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3130 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3131 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3132 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3133 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3134 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3135 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3136 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3137 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3138 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3139 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3140 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3141 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3142 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3143 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3144 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3145 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3146 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3147 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3148 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3149 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3150 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3151 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3152 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3153 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3154 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3155 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3156 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3157 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3159 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3160 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3161 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3162 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3163 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3164 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3165 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3166 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3167 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3168 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3169 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3170 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3171 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3172 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3173 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3174 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3175 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3176 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3177 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3178 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3179 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3180 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3181 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3213 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3214 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3263 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); in ingenic_gpio_read_reg()
3271 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { in ingenic_gpio_set_bit()
3272 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, in ingenic_gpio_set_bit()
3282 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); in ingenic_gpio_set_bit()
3293 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( in ingenic_gpio_shadow_set_bit()
3294 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); in ingenic_gpio_shadow_set_bit()
3299 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( in ingenic_gpio_shadow_set_bit_load()
3300 jzgc->jzpc->info->reg_offset), in ingenic_gpio_shadow_set_bit_load()
3301 jzgc->gc.base / PINS_PER_GPIO_CHIP); in ingenic_gpio_shadow_set_bit_load()
3308 * JZ4730 function and IRQ registers support two-bits-per-pin in jz4730_gpio_set_bits()
3315 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); in jz4730_gpio_set_bits()
3329 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) in ingenic_gpio_set_value()
3331 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_set_value()
3366 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) { in irq_set_type()
3369 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { in irq_set_type()
3379 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) { in irq_set_type()
3384 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) { in irq_set_type()
3400 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_mask()
3412 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_unmask()
3426 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) in ingenic_gpio_irq_enable()
3428 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_enable()
3444 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) in ingenic_gpio_irq_disable()
3446 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_disable()
3462 !is_soc_or_above(jzgc->jzpc, ID_X2000)) { in ingenic_gpio_irq_ack()
3474 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) in ingenic_gpio_irq_ack()
3476 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_ack()
3502 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) { in ingenic_gpio_irq_set_type()
3505 * best we can do is to set up a single-edge interrupt and then in ingenic_gpio_irq_set_type()
3522 return irq_set_irq_wake(jzgc->irq, on); in ingenic_gpio_irq_set_wake()
3529 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_gpio_irq_handler()
3534 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) in ingenic_gpio_irq_handler()
3536 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) in ingenic_gpio_irq_handler()
3542 generic_handle_domain_irq(gc->irq.domain, i); in ingenic_gpio_irq_handler()
3564 return pinctrl_gpio_direction_input(gc->base + offset); in ingenic_gpio_direction_input()
3571 return pinctrl_gpio_direction_output(gc->base + offset); in ingenic_gpio_direction_output()
3582 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3585 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3589 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3592 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3602 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + in ingenic_shadow_config_pin()
3609 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), in ingenic_shadow_config_pin_load()
3617 * JZ4730 function and IRQ registers support two-bits-per-pin in jz4730_config_pin_function()
3625 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, in jz4730_config_pin_function()
3636 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); in ingenic_get_pin_config()
3644 struct ingenic_pinctrl *jzpc = jzgc->jzpc; in ingenic_gpio_get_direction()
3645 unsigned int pin = gc->base + offset; in ingenic_gpio_get_direction()
3700 seq_printf(p, "%s", gpio_chip->label); in ingenic_gpio_irq_print_chip()
3723 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", in ingenic_pinmux_set_pin_fn()
3761 return -EINVAL; in ingenic_pinmux_set_mux()
3765 return -EINVAL; in ingenic_pinmux_set_mux()
3767 dev_dbg(pctldev->dev, "enable function %s group %s\n", in ingenic_pinmux_set_mux()
3768 func->name, grp->name); in ingenic_pinmux_set_mux()
3770 mode = (uintptr_t)grp->data; in ingenic_pinmux_set_mux()
3771 if (mode <= 3) { in ingenic_pinmux_set_mux()
3772 for (i = 0; i < grp->num_pins; i++) in ingenic_pinmux_set_mux()
3773 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); in ingenic_pinmux_set_mux()
3775 pin_modes = grp->data; in ingenic_pinmux_set_mux()
3777 for (i = 0; i < grp->num_pins; i++) in ingenic_pinmux_set_mux()
3778 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); in ingenic_pinmux_set_mux()
3792 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", in ingenic_pinmux_gpio_set_direction()
3839 (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3842 (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3849 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_pinconf_get()
3852 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_pinconf_get()
3857 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3858 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3868 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3869 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3875 return -EINVAL; in ingenic_pinconf_get()
3881 return -EINVAL; in ingenic_pinconf_get()
3887 return -EINVAL; in ingenic_pinconf_get()
3897 return -EINVAL; in ingenic_pinconf_get()
3908 return -EINVAL; in ingenic_pinconf_get()
3914 return -ENOTSUPP; in ingenic_pinconf_get()
3949 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3950 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); in ingenic_set_bias()
3951 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3954 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3955 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); in ingenic_set_bias()
3956 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
4017 return -ENOTSUPP; in ingenic_pinconf_set()
4026 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", in ingenic_pinconf_set()
4032 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) in ingenic_pinconf_set()
4033 return -EINVAL; in ingenic_pinconf_set()
4034 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", in ingenic_pinconf_set()
4040 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) in ingenic_pinconf_set()
4041 return -EINVAL; in ingenic_pinconf_set()
4042 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", in ingenic_pinconf_set()
4049 return -EINVAL; in ingenic_pinconf_set()
4064 return -EINVAL; in ingenic_pinconf_set()
4091 return -ENOTSUPP; in ingenic_pinconf_group_get()
4095 return -ENOTSUPP; in ingenic_pinconf_group_get()
4140 { .compatible = "ingenic,jz4730-gpio" },
4141 { .compatible = "ingenic,jz4740-gpio" },
4142 { .compatible = "ingenic,jz4725b-gpio" },
4143 { .compatible = "ingenic,jz4750-gpio" },
4144 { .compatible = "ingenic,jz4755-gpio" },
4145 { .compatible = "ingenic,jz4760-gpio" },
4146 { .compatible = "ingenic,jz4770-gpio" },
4147 { .compatible = "ingenic,jz4775-gpio" },
4148 { .compatible = "ingenic,jz4780-gpio" },
4149 { .compatible = "ingenic,x1000-gpio" },
4150 { .compatible = "ingenic,x1830-gpio" },
4151 { .compatible = "ingenic,x2000-gpio" },
4152 { .compatible = "ingenic,x2100-gpio" },
4160 struct device *dev = jzpc->dev; in ingenic_gpio_probe()
4173 return -ENOMEM; in ingenic_gpio_probe()
4175 jzgc->jzpc = jzpc; in ingenic_gpio_probe()
4176 jzgc->reg_base = bank * jzpc->info->reg_offset; in ingenic_gpio_probe()
4178 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); in ingenic_gpio_probe()
4179 if (!jzgc->gc.label) in ingenic_gpio_probe()
4180 return -ENOMEM; in ingenic_gpio_probe()
4186 jzgc->gc.base = bank * 32; in ingenic_gpio_probe()
4188 jzgc->gc.ngpio = 32; in ingenic_gpio_probe()
4189 jzgc->gc.parent = dev; in ingenic_gpio_probe()
4190 jzgc->gc.fwnode = fwnode; in ingenic_gpio_probe()
4191 jzgc->gc.owner = THIS_MODULE; in ingenic_gpio_probe()
4193 jzgc->gc.set = ingenic_gpio_set; in ingenic_gpio_probe()
4194 jzgc->gc.get = ingenic_gpio_get; in ingenic_gpio_probe()
4195 jzgc->gc.direction_input = ingenic_gpio_direction_input; in ingenic_gpio_probe()
4196 jzgc->gc.direction_output = ingenic_gpio_direction_output; in ingenic_gpio_probe()
4197 jzgc->gc.get_direction = ingenic_gpio_get_direction; in ingenic_gpio_probe()
4198 jzgc->gc.request = gpiochip_generic_request; in ingenic_gpio_probe()
4199 jzgc->gc.free = gpiochip_generic_free; in ingenic_gpio_probe()
4205 return -EINVAL; in ingenic_gpio_probe()
4206 jzgc->irq = err; in ingenic_gpio_probe()
4208 girq = &jzgc->gc.irq; in ingenic_gpio_probe()
4210 girq->parent_handler = ingenic_gpio_irq_handler; in ingenic_gpio_probe()
4211 girq->num_parents = 1; in ingenic_gpio_probe()
4212 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in ingenic_gpio_probe()
4214 if (!girq->parents) in ingenic_gpio_probe()
4215 return -ENOMEM; in ingenic_gpio_probe()
4217 girq->parents[0] = jzgc->irq; in ingenic_gpio_probe()
4218 girq->default_type = IRQ_TYPE_NONE; in ingenic_gpio_probe()
4219 girq->handler = handle_level_irq; in ingenic_gpio_probe()
4221 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); in ingenic_gpio_probe()
4230 struct device *dev = &pdev->dev; in ingenic_pinctrl_probe()
4243 return -EINVAL; in ingenic_pinctrl_probe()
4248 return -ENOMEM; in ingenic_pinctrl_probe()
4255 if (chip_info->access_table) { in ingenic_pinctrl_probe()
4256 regmap_config.rd_table = chip_info->access_table; in ingenic_pinctrl_probe()
4257 regmap_config.wr_table = chip_info->access_table; in ingenic_pinctrl_probe()
4259 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; in ingenic_pinctrl_probe()
4262 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); in ingenic_pinctrl_probe()
4263 if (IS_ERR(jzpc->map)) { in ingenic_pinctrl_probe()
4265 return PTR_ERR(jzpc->map); in ingenic_pinctrl_probe()
4268 jzpc->dev = dev; in ingenic_pinctrl_probe()
4269 jzpc->info = chip_info; in ingenic_pinctrl_probe()
4271 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); in ingenic_pinctrl_probe()
4273 return -ENOMEM; in ingenic_pinctrl_probe()
4276 pctl_desc->name = dev_name(dev); in ingenic_pinctrl_probe()
4277 pctl_desc->owner = THIS_MODULE; in ingenic_pinctrl_probe()
4278 pctl_desc->pctlops = &ingenic_pctlops; in ingenic_pinctrl_probe()
4279 pctl_desc->pmxops = &ingenic_pmxops; in ingenic_pinctrl_probe()
4280 pctl_desc->confops = &ingenic_confops; in ingenic_pinctrl_probe()
4281 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; in ingenic_pinctrl_probe()
4282 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, in ingenic_pinctrl_probe()
4283 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); in ingenic_pinctrl_probe()
4284 if (!jzpc->pdesc) in ingenic_pinctrl_probe()
4285 return -ENOMEM; in ingenic_pinctrl_probe()
4287 for (i = 0; i < pctl_desc->npins; i++) { in ingenic_pinctrl_probe()
4288 jzpc->pdesc[i].number = i; in ingenic_pinctrl_probe()
4289 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", in ingenic_pinctrl_probe()
4294 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); in ingenic_pinctrl_probe()
4295 if (IS_ERR(jzpc->pctl)) { in ingenic_pinctrl_probe()
4297 return PTR_ERR(jzpc->pctl); in ingenic_pinctrl_probe()
4300 for (i = 0; i < chip_info->num_groups; i++) { in ingenic_pinctrl_probe()
4301 const struct group_desc *group = &chip_info->groups[i]; in ingenic_pinctrl_probe()
4303 err = pinctrl_generic_add_group(jzpc->pctl, group->name, in ingenic_pinctrl_probe()
4304 group->pins, group->num_pins, group->data); in ingenic_pinctrl_probe()
4307 group->name); in ingenic_pinctrl_probe()
4312 for (i = 0; i < chip_info->num_functions; i++) { in ingenic_pinctrl_probe()
4313 const struct function_desc *func = &chip_info->functions[i]; in ingenic_pinctrl_probe()
4315 err = pinmux_generic_add_function(jzpc->pctl, func->name, in ingenic_pinctrl_probe()
4316 func->group_names, func->num_group_names, in ingenic_pinctrl_probe()
4317 func->data); in ingenic_pinctrl_probe()
4320 func->name); in ingenic_pinctrl_probe()
4325 dev_set_drvdata(dev, jzpc->map); in ingenic_pinctrl_probe()
4344 .compatible = "ingenic,jz4730-pinctrl",
4348 .compatible = "ingenic,jz4740-pinctrl",
4352 .compatible = "ingenic,jz4725b-pinctrl",
4356 .compatible = "ingenic,jz4750-pinctrl",
4360 .compatible = "ingenic,jz4755-pinctrl",
4364 .compatible = "ingenic,jz4760-pinctrl",
4368 .compatible = "ingenic,jz4760b-pinctrl",
4372 .compatible = "ingenic,jz4770-pinctrl",
4376 .compatible = "ingenic,jz4775-pinctrl",
4380 .compatible = "ingenic,jz4780-pinctrl",
4384 .compatible = "ingenic,x1000-pinctrl",
4388 .compatible = "ingenic,x1000e-pinctrl",
4392 .compatible = "ingenic,x1500-pinctrl",
4396 .compatible = "ingenic,x1830-pinctrl",
4400 .compatible = "ingenic,x2000-pinctrl",
4404 .compatible = "ingenic,x2000e-pinctrl",
4408 .compatible = "ingenic,x2100-pinctrl",
4416 .name = "pinctrl-ingenic",