Lines Matching refs:DRV_BASE2
18 #define DRV_BASE2 0x510 macro
86 MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
87 MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
88 MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
89 MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
90 MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
91 MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
92 MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
93 MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
94 MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
95 MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
96 MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
97 MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
99 MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
100 MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
101 MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
102 MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
103 MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
104 MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
105 MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
106 MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
108 MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
109 MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
110 MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
111 MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
112 MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
113 MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
114 MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
115 MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
116 MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
117 MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
118 MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
119 MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
120 MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
122 MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
123 MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
124 MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
125 MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
126 MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
127 MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
128 MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
129 MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
130 MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
132 MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
133 MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
135 MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
136 MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
138 MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
139 MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
140 MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
141 MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
142 MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
143 MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
145 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
146 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
147 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
148 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
149 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
150 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
151 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
155 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
156 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
157 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
158 MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
159 MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
162 MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
163 MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
164 MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
165 MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
166 MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
167 MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
168 MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
169 MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
170 MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
171 MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
172 MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
174 MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
175 MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
176 MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
177 MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
178 MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
179 MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),