pinctrl/mediatek/pinctrl-mt7986.c

1 // SPDX-License-Identifier: GPL-2.0
9 #include "pinctrl-moore.h"
20  * enum - Locking variants of the iocfg bases
33  *    +------------------------+
42  *    +------------------------+
47  *    +------------------------+
50  *  6 |      +---------+       |
54  *  2 |      +---------+       |
56  *    +------------------------+
104 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
109 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
158 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
163 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
253 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
258 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
309 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
314 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
347 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
352 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
385 	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
390 	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
426 	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
428 	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
510 	MT7986_PIN(30, "SPI1_MOSI"),
515 	MT7986_PIN(35, "SPI2_MISO"),
614 	MT7986_PIN(30, "SPI1_MOSI"),
619 	MT7986_PIN(35, "SPI2_MISO"),
717 	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
729 static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
732 static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
738 static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
744 static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
750 static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
753 static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
759 static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
965 	{.compatible = "mediatek,mt7986a-pinctrl",},
970 	{.compatible = "mediatek,mt7986b-pinctrl",},
986 		.name = "mt7986a-pinctrl",
994 		.name = "mt7986b-pinctrl",