246 	u32 value;  in lp_gpio_ioxapic_use()  local
248 	value = ioread32(ioxapic_use);  in lp_gpio_ioxapic_use()
251 		return !!(value & BIT(offset -  8 + 0));  in lp_gpio_ioxapic_use()
253 		return !!(value & BIT(offset - 13 + 3));  in lp_gpio_ioxapic_use()
255 		return !!(value & BIT(offset - 45 + 5));  in lp_gpio_ioxapic_use()
266 	u32 value, mode;  in lp_pin_dbg_show()  local
268 	value = ioread32(reg);  in lp_pin_dbg_show()
270 	mode = value & USE_SEL_MASK;  in lp_pin_dbg_show()
276 	seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));  in lp_pin_dbg_show()
302 		u32 value;  in lp_pinmux_set_mux()  local
304 		value = ioread32(reg);  in lp_pinmux_set_mux()
306 		value &= ~USE_SEL_MASK;  in lp_pinmux_set_mux()
308 			value |= grp->modes[i];  in lp_pinmux_set_mux()
310 			value |= grp->mode;  in lp_pinmux_set_mux()
312 		iowrite32(value, reg);  in lp_pinmux_set_mux()
338 	u32 value;  in lp_gpio_request_enable()  local
348 	value = ioread32(reg);  in lp_gpio_request_enable()
349 	if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {  in lp_gpio_request_enable()
350 		iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);  in lp_gpio_request_enable()
387 	u32 value;  in lp_gpio_set_direction()  local
391 	value = ioread32(reg);  in lp_gpio_set_direction()
392 	value &= ~DIR_BIT;  in lp_gpio_set_direction()
394 		value |= DIR_BIT;  in lp_gpio_set_direction()
405 	iowrite32(value, reg);  in lp_gpio_set_direction()
429 	u32 value, pull;  in lp_pin_config_get()  local
433 	value = ioread32(conf2);  in lp_pin_config_get()
436 	pull = value & GPIWP_MASK;  in lp_pin_config_get()
473 	u32 value;  in lp_pin_config_set()  local
477 	value = ioread32(conf2);  in lp_pin_config_set()
484 			value &= ~GPIWP_MASK;  in lp_pin_config_set()
485 			value |= GPIWP_NONE;  in lp_pin_config_set()
488 			value &= ~GPIWP_MASK;  in lp_pin_config_set()
489 			value |= GPIWP_DOWN;  in lp_pin_config_set()
492 			value &= ~GPIWP_MASK;  in lp_pin_config_set()
493 			value |= GPIWP_UP;  in lp_pin_config_set()
504 		iowrite32(value, conf2);  in lp_pin_config_set()
530 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)  in lp_gpio_set()  argument
538 	if (value)  in lp_gpio_set()
552 				    int value)  in lp_gpio_direction_output()  argument
554 	lp_gpio_set(chip, offset, value);  in lp_gpio_direction_output()
651 	u32 value;  in lp_irq_set_type()  local
664 	value = ioread32(reg);  in lp_irq_set_type()
668 		value &= ~(TRIG_SEL_BIT | INT_INV_BIT);  in lp_irq_set_type()
672 		value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;  in lp_irq_set_type()
676 		value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;  in lp_irq_set_type()
680 		value |= TRIG_SEL_BIT | INT_INV_BIT;  in lp_irq_set_type()
682 	iowrite32(value, reg);  in lp_irq_set_type()