578 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)  in chv_pctrl_writel()  argument
584 	writel(value, reg);  in chv_pctrl_writel()
605 …atic void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)  in chv_writel()  argument
610 	writel(value, reg);  in chv_writel()
686 		u32 value;  in chv_pinmux_set_mux()  local
698 		value = chv_readl(pctrl, pin, CHV_PADCTRL0);  in chv_pinmux_set_mux()
700 		value &= ~CHV_PADCTRL0_GPIOEN;  in chv_pinmux_set_mux()
702 		value &= ~CHV_PADCTRL0_PMODE_MASK;  in chv_pinmux_set_mux()
703 		value |= mode << CHV_PADCTRL0_PMODE_SHIFT;  in chv_pinmux_set_mux()
704 		chv_writel(pctrl, pin, CHV_PADCTRL0, value);  in chv_pinmux_set_mux()
707 		value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;  in chv_pinmux_set_mux()
709 			value |= CHV_PADCTRL1_INVRXTX_TXENABLE;  in chv_pinmux_set_mux()
710 		chv_writel(pctrl, pin, CHV_PADCTRL1, value);  in chv_pinmux_set_mux()
725 	u32 value;  in chv_gpio_clear_triggering()  local
733 	value = chv_readl(pctrl, offset, CHV_PADCTRL0);  in chv_gpio_clear_triggering()
734 	if (value & CHV_PADCTRL0_GPIOEN)  in chv_gpio_clear_triggering()
737 	value = chv_readl(pctrl, offset, CHV_PADCTRL1);  in chv_gpio_clear_triggering()
738 	value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;  in chv_gpio_clear_triggering()
739 	value &= ~invrxtx_mask;  in chv_gpio_clear_triggering()
740 	chv_writel(pctrl, offset, CHV_PADCTRL1, value);  in chv_gpio_clear_triggering()
749 	u32 value;  in chv_gpio_request_enable()  local
754 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);  in chv_gpio_request_enable()
755 		if (!(value & CHV_PADCTRL0_GPIOEN)) {  in chv_gpio_request_enable()
775 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);  in chv_gpio_request_enable()
781 		if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==  in chv_gpio_request_enable()
783 			value &= ~CHV_PADCTRL0_GPIOCFG_MASK;  in chv_gpio_request_enable()
784 			value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;  in chv_gpio_request_enable()
788 		value |= CHV_PADCTRL0_GPIOEN;  in chv_gpio_request_enable()
789 		chv_writel(pctrl, offset, CHV_PADCTRL0, value);  in chv_gpio_request_enable()
1134 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)  in chv_gpio_set()  argument
1144 	if (value)  in chv_gpio_set()
1179 				     int value)  in chv_gpio_direction_output()  argument
1181 	chv_gpio_set(chip, offset, value);  in chv_gpio_direction_output()
1216 	u32 value, intr_line;  in chv_gpio_irq_mask_unmask()  local
1225 	value = chv_pctrl_readl(pctrl, CHV_INTMASK);  in chv_gpio_irq_mask_unmask()
1227 		value &= ~BIT(intr_line);  in chv_gpio_irq_mask_unmask()
1229 		value |= BIT(intr_line);  in chv_gpio_irq_mask_unmask()
1230 	chv_pctrl_writel(pctrl, CHV_INTMASK, value);  in chv_gpio_irq_mask_unmask()
1273 		u32 intsel, value;  in chv_gpio_irq_startup()  local
1280 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);  in chv_gpio_irq_startup()
1281 		if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)  in chv_gpio_irq_startup()
1304 	u32 value, intsel;  in chv_gpio_set_intr_line()  local
1307 	value = chv_readl(pctrl, pin, CHV_PADCTRL0);  in chv_gpio_set_intr_line()
1308 	intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;  in chv_gpio_set_intr_line()
1345 	value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);  in chv_gpio_set_intr_line()
1346 	chv_writel(pctrl, pin, CHV_PADCTRL0, value);  in chv_gpio_set_intr_line()
1358 	u32 value;  in chv_gpio_irq_type()  local
1383 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);  in chv_gpio_irq_type()
1384 		value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;  in chv_gpio_irq_type()
1385 		value &= ~CHV_PADCTRL1_INVRXTX_MASK;  in chv_gpio_irq_type()
1389 				value |= CHV_PADCTRL1_INTWAKECFG_BOTH;  in chv_gpio_irq_type()
1391 				value |= CHV_PADCTRL1_INTWAKECFG_RISING;  in chv_gpio_irq_type()
1393 				value |= CHV_PADCTRL1_INTWAKECFG_FALLING;  in chv_gpio_irq_type()
1395 			value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;  in chv_gpio_irq_type()
1397 				value |= CHV_PADCTRL1_INVRXTX_RXDATA;  in chv_gpio_irq_type()
1400 		chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);  in chv_gpio_irq_type()
1625 	acpi_physical_address address, u32 bits, u64 *value,  in chv_pinctrl_mmio_access_handler()  argument
1635 		chv_pctrl_writel(pctrl, address, *value);  in chv_pinctrl_mmio_access_handler()
1637 		*value = chv_pctrl_readl(pctrl, address);  in chv_pinctrl_mmio_access_handler()