Lines Matching refs:using

22 	  allows configuring of SoC pins and using them as GPIOs.
30 	  using them as GPIOs.
45 	  of Intel Alder Lake PCH pins and using them as GPIOs.
52 	  configuring of SoC pins and using them as GPIOs.
59 	  of Intel Cannon Lake PCH pins and using them as GPIOs.
66 	  of Intel Cedar Fork PCH pins and using them as GPIOs.
73 	  of Intel Denverton SoC pins and using them as GPIOs.
80 	  of Intel Elkhart Lake SoC pins and using them as GPIOs.
87 	  of Intel Emmitsburg pins and using them as GPIOs.
94 	  of Intel Gemini Lake SoC pins and using them as GPIOs.
101 	  of Intel Ice Lake PCH pins and using them as GPIOs.
108 	  of Intel Jasper Lake PCH pins and using them as GPIOs.
115 	  of Intel Lakefield SoC pins and using them as GPIOs.
122 	  of Intel Lewisburg pins and using them as GPIOs.
129 	  of Intel Meteor Lake pins and using them as GPIOs.
137 	  using them as GPIOs.
144 	  of Intel Tiger Lake PCH pins and using them as GPIOs.