Lines Matching +full:cmn +full:- +full:refclk1 +full:- +full:dig +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
127 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
128 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
253 .node_name = "pll0-refclk",
257 .node_name = "pll1-refclk",
261 .node_name = "refclk-dig",
274 .node_name = "pll0-refclk",
280 .node_name = "pll1-refclk",
286 .node_name = "refclk-dig",
295 .node_name = "pll0-refclk",
301 .node_name = "pll1-refclk",
307 .node_name = "refclk-dig",
312 { .val = 0, .div = 1, },
313 { .val = 1, .div = 2, },
314 { .val = 2, .div = 4, },
315 { .val = 3, .div = 8, },
322 .node_name = "cmn-refclk-dig-div",
326 .node_name = "cmn-refclk1-dig-div",
402 ret = regmap_field_write(wiz->por_en, 0x1); in wiz_reset()
408 ret = regmap_field_write(wiz->por_en, 0x0); in wiz_reset()
417 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel()
422 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || in wiz_p_mac_div_sel()
423 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || in wiz_p_mac_div_sel()
424 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { in wiz_p_mac_div_sel()
425 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); in wiz_p_mac_div_sel()
429 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); in wiz_p_mac_div_sel()
440 u32 num_lanes = wiz->num_lanes; in wiz_mode_select()
446 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) { in wiz_mode_select()
448 } else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { in wiz_mode_select()
450 } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { in wiz_mode_select()
451 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); in wiz_mode_select()
452 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); in wiz_mode_select()
453 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); in wiz_mode_select()
459 ret = regmap_field_write(wiz->p_standard_mode[i], mode); in wiz_mode_select()
469 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface()
474 ret = regmap_field_write(wiz->p_align[i], enable); in wiz_init_raw_interface()
478 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); in wiz_init_raw_interface()
488 struct device *dev = wiz->dev; in wiz_init()
505 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); in wiz_init()
520 struct regmap *regmap = wiz->regmap; in wiz_regfield_init()
521 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ in wiz_regfield_init()
522 int num_lanes = wiz->num_lanes; in wiz_regfield_init()
523 struct device *dev = wiz->dev; in wiz_regfield_init()
524 const struct wiz_data *data = wiz->data; in wiz_regfield_init()
527 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); in wiz_regfield_init()
528 if (IS_ERR(wiz->por_en)) { in wiz_regfield_init()
530 return PTR_ERR(wiz->por_en); in wiz_regfield_init()
533 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
535 if (IS_ERR(wiz->phy_reset_n)) { in wiz_regfield_init()
537 return PTR_ERR(wiz->phy_reset_n); in wiz_regfield_init()
540 wiz->pma_cmn_refclk_int_mode = in wiz_regfield_init()
542 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { in wiz_regfield_init()
544 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); in wiz_regfield_init()
547 wiz->pma_cmn_refclk_mode = in wiz_regfield_init()
549 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { in wiz_regfield_init()
551 return PTR_ERR(wiz->pma_cmn_refclk_mode); in wiz_regfield_init()
554 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = in wiz_regfield_init()
556 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { in wiz_regfield_init()
558 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); in wiz_regfield_init()
561 if (data->pma_cmn_refclk1_dig_div) { in wiz_regfield_init()
562 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = in wiz_regfield_init()
564 *data->pma_cmn_refclk1_dig_div); in wiz_regfield_init()
565 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { in wiz_regfield_init()
567 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); in wiz_regfield_init()
571 if (wiz->scm_regmap) { in wiz_regfield_init()
572 scm_regmap = wiz->scm_regmap; in wiz_regfield_init()
573 wiz->sup_legacy_clk_override = in wiz_regfield_init()
575 if (IS_ERR(wiz->sup_legacy_clk_override)) { in wiz_regfield_init()
577 return PTR_ERR(wiz->sup_legacy_clk_override); in wiz_regfield_init()
581 wiz->mux_sel_field[PLL0_REFCLK] = in wiz_regfield_init()
582 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); in wiz_regfield_init()
583 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { in wiz_regfield_init()
585 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); in wiz_regfield_init()
588 wiz->mux_sel_field[PLL1_REFCLK] = in wiz_regfield_init()
589 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); in wiz_regfield_init()
590 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { in wiz_regfield_init()
592 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); in wiz_regfield_init()
595 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, in wiz_regfield_init()
596 *data->refclk_dig_sel); in wiz_regfield_init()
597 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { in wiz_regfield_init()
599 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); in wiz_regfield_init()
602 if (data->pma_cmn_refclk1_int_mode) { in wiz_regfield_init()
603 wiz->pma_cmn_refclk1_int_mode = in wiz_regfield_init()
604 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); in wiz_regfield_init()
605 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { in wiz_regfield_init()
607 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); in wiz_regfield_init()
612 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
614 if (IS_ERR(wiz->p_enable[i])) { in wiz_regfield_init()
616 return PTR_ERR(wiz->p_enable[i]); in wiz_regfield_init()
619 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
621 if (IS_ERR(wiz->p_align[i])) { in wiz_regfield_init()
623 return PTR_ERR(wiz->p_align[i]); in wiz_regfield_init()
626 wiz->p_raw_auto_start[i] = in wiz_regfield_init()
628 if (IS_ERR(wiz->p_raw_auto_start[i])) { in wiz_regfield_init()
631 return PTR_ERR(wiz->p_raw_auto_start[i]); in wiz_regfield_init()
634 wiz->p_standard_mode[i] = in wiz_regfield_init()
636 if (IS_ERR(wiz->p_standard_mode[i])) { in wiz_regfield_init()
639 return PTR_ERR(wiz->p_standard_mode[i]); in wiz_regfield_init()
642 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); in wiz_regfield_init()
643 if (IS_ERR(wiz->p0_fullrt_div[i])) { in wiz_regfield_init()
645 return PTR_ERR(wiz->p0_fullrt_div[i]); in wiz_regfield_init()
648 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); in wiz_regfield_init()
649 if (IS_ERR(wiz->p0_mac_src_sel[i])) { in wiz_regfield_init()
651 return PTR_ERR(wiz->p0_mac_src_sel[i]); in wiz_regfield_init()
654 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); in wiz_regfield_init()
655 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { in wiz_regfield_init()
657 return PTR_ERR(wiz->p0_rxfclk_sel[i]); in wiz_regfield_init()
660 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); in wiz_regfield_init()
661 if (IS_ERR(wiz->p0_refclk_sel[i])) { in wiz_regfield_init()
663 return PTR_ERR(wiz->p0_refclk_sel[i]); in wiz_regfield_init()
666 wiz->p_mac_div_sel0[i] = in wiz_regfield_init()
668 if (IS_ERR(wiz->p_mac_div_sel0[i])) { in wiz_regfield_init()
671 return PTR_ERR(wiz->p_mac_div_sel0[i]); in wiz_regfield_init()
674 wiz->p_mac_div_sel1[i] = in wiz_regfield_init()
676 if (IS_ERR(wiz->p_mac_div_sel1[i])) { in wiz_regfield_init()
679 return PTR_ERR(wiz->p_mac_div_sel1[i]); in wiz_regfield_init()
683 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
685 if (IS_ERR(wiz->typec_ln10_swap)) { in wiz_regfield_init()
687 return PTR_ERR(wiz->typec_ln10_swap); in wiz_regfield_init()
690 wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
692 if (IS_ERR(wiz->typec_ln23_swap)) { in wiz_regfield_init()
694 return PTR_ERR(wiz->typec_ln23_swap); in wiz_regfield_init()
697 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); in wiz_regfield_init()
698 if (IS_ERR(wiz->phy_en_refclk)) { in wiz_regfield_init()
700 return PTR_ERR(wiz->phy_en_refclk); in wiz_regfield_init()
709 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_enable()
719 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_disable()
727 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_is_enabled()
744 struct device *dev = wiz->dev; in wiz_phy_en_refclk_register()
752 return -ENOMEM; in wiz_phy_en_refclk_register()
754 init = &wiz_phy_en_refclk->clk_data; in wiz_phy_en_refclk_register()
756 init->ops = &wiz_phy_en_refclk_ops; in wiz_phy_en_refclk_register()
757 init->flags = 0; in wiz_phy_en_refclk_register()
763 return -ENOMEM; in wiz_phy_en_refclk_register()
766 init->name = clk_name; in wiz_phy_en_refclk_register()
768 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; in wiz_phy_en_refclk_register()
769 wiz_phy_en_refclk->hw.init = init; in wiz_phy_en_refclk_register()
771 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); in wiz_phy_en_refclk_register()
778 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; in wiz_phy_en_refclk_register()
786 struct regmap_field *field = mux->field; in wiz_clk_mux_get_parent()
790 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); in wiz_clk_mux_get_parent()
796 struct regmap_field *field = mux->field; in wiz_clk_mux_set_parent()
799 val = mux->table[index]; in wiz_clk_mux_set_parent()
812 struct device *dev = wiz->dev; in wiz_mux_clk_register()
823 return -ENOMEM; in wiz_mux_clk_register()
825 num_parents = mux_sel->num_parents; in wiz_mux_clk_register()
829 return -ENOMEM; in wiz_mux_clk_register()
832 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()
836 ret = -EINVAL; in wiz_mux_clk_register()
844 init = &mux->clk_data; in wiz_mux_clk_register()
846 init->ops = &wiz_clk_mux_ops; in wiz_mux_clk_register()
847 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_clk_register()
848 init->parent_names = parent_names; in wiz_mux_clk_register()
849 init->num_parents = num_parents; in wiz_mux_clk_register()
850 init->name = clk_name; in wiz_mux_clk_register()
852 mux->field = field; in wiz_mux_clk_register()
853 mux->table = mux_sel->table; in wiz_mux_clk_register()
854 mux->hw.init = init; in wiz_mux_clk_register()
856 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_clk_register()
862 wiz->output_clks[clk_index] = clk; in wiz_mux_clk_register()
873 struct device *dev = wiz->dev; in wiz_mux_of_clk_register()
884 return -ENOMEM; in wiz_mux_of_clk_register()
889 return -EINVAL; in wiz_mux_of_clk_register()
895 return -ENOMEM; in wiz_mux_of_clk_register()
900 node->name); in wiz_mux_of_clk_register()
902 init = &mux->clk_data; in wiz_mux_of_clk_register()
904 init->ops = &wiz_clk_mux_ops; in wiz_mux_of_clk_register()
905 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_of_clk_register()
906 init->parent_names = parent_names; in wiz_mux_of_clk_register()
907 init->num_parents = num_parents; in wiz_mux_of_clk_register()
908 init->name = clk_name; in wiz_mux_of_clk_register()
910 mux->field = field; in wiz_mux_of_clk_register()
911 mux->table = table; in wiz_mux_of_clk_register()
912 mux->hw.init = init; in wiz_mux_of_clk_register()
914 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_of_clk_register()
928 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_recalc_rate() local
929 struct regmap_field *field = div->field; in wiz_clk_div_recalc_rate()
934 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); in wiz_clk_div_recalc_rate()
940 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_round_rate() local
942 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); in wiz_clk_div_round_rate()
948 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_set_rate() local
949 struct regmap_field *field = div->field; in wiz_clk_div_set_rate()
952 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); in wiz_clk_div_set_rate()
969 struct device *dev = wiz->dev; in wiz_div_clk_register()
970 struct wiz_clk_divider *div; in wiz_div_clk_register() local
977 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in wiz_div_clk_register()
978 if (!div) in wiz_div_clk_register()
979 return -ENOMEM; in wiz_div_clk_register()
982 node->name); in wiz_div_clk_register()
986 return -ENOMEM; in wiz_div_clk_register()
990 init = &div->clk_data; in wiz_div_clk_register()
992 init->ops = &wiz_clk_div_ops; in wiz_div_clk_register()
993 init->flags = 0; in wiz_div_clk_register()
994 init->parent_names = parent_names; in wiz_div_clk_register()
995 init->num_parents = 1; in wiz_div_clk_register()
996 init->name = clk_name; in wiz_div_clk_register()
998 div->field = field; in wiz_div_clk_register()
999 div->table = table; in wiz_div_clk_register()
1000 div->hw.init = init; in wiz_div_clk_register()
1002 clk = devm_clk_register(dev, &div->hw); in wiz_div_clk_register()
1015 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_cleanup()
1016 struct device *dev = wiz->dev; in wiz_clock_cleanup()
1020 switch (wiz->type) { in wiz_clock_cleanup()
1025 of_clk_del_provider(dev->of_node); in wiz_clock_cleanup()
1037 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_cleanup()
1043 of_clk_del_provider(wiz->dev->of_node); in wiz_clock_cleanup()
1048 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_register()
1049 struct device *dev = wiz->dev; in wiz_clock_register()
1050 struct device_node *node = dev->of_node; in wiz_clock_register()
1057 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); in wiz_clock_register()
1066 dev_err(dev, "Failed to add phy-en-refclk\n"); in wiz_clock_register()
1070 wiz->clk_data.clks = wiz->output_clks; in wiz_clock_register()
1071 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; in wiz_clock_register()
1072 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); in wiz_clock_register()
1074 dev_err(dev, "Failed to add clock provider: %s\n", node->name); in wiz_clock_register()
1081 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_init()
1082 struct device *dev = wiz->dev; in wiz_clock_init()
1096 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_init()
1100 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); in wiz_clock_init()
1102 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); in wiz_clock_init()
1104 switch (wiz->type) { in wiz_clock_init()
1109 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); in wiz_clock_init()
1112 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); in wiz_clock_init()
1115 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); in wiz_clock_init()
1123 if (wiz->data->pma_cmn_refclk1_int_mode) { in wiz_clock_init()
1130 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; in wiz_clock_init()
1134 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); in wiz_clock_init()
1136 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); in wiz_clock_init()
1145 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_init()
1149 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); in wiz_clock_init()
1151 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); in wiz_clock_init()
1153 switch (wiz->type) { in wiz_clock_init()
1171 ret = -EINVAL; in wiz_clock_init()
1175 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], in wiz_clock_init()
1187 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_init()
1192 ret = -EINVAL; in wiz_clock_init()
1196 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], in wiz_clock_init()
1218 struct device *dev = rcdev->dev; in wiz_phy_reset_assert()
1223 ret = regmap_field_write(wiz->phy_reset_n, false); in wiz_phy_reset_assert()
1227 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); in wiz_phy_reset_assert()
1233 switch (wiz->type) { in wiz_phy_fullrt_div()
1235 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) in wiz_phy_fullrt_div()
1236 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); in wiz_phy_fullrt_div()
1243 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) in wiz_phy_fullrt_div()
1244 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); in wiz_phy_fullrt_div()
1255 struct device *dev = rcdev->dev; in wiz_phy_reset_deassert()
1260 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ in wiz_phy_reset_deassert()
1261 if (wiz->gpio_typec_dir) { in wiz_phy_reset_deassert()
1262 if (wiz->typec_dir_delay) in wiz_phy_reset_deassert()
1263 msleep_interruptible(wiz->typec_dir_delay); in wiz_phy_reset_deassert()
1265 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) in wiz_phy_reset_deassert()
1266 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
1268 regmap_field_write(wiz->typec_ln10_swap, 0); in wiz_phy_reset_deassert()
1270 /* if no typec-dir gpio is specified and PHY type is USB3 in wiz_phy_reset_deassert()
1274 u32 num_lanes = wiz->num_lanes; in wiz_phy_reset_deassert()
1278 if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { in wiz_phy_reset_deassert()
1279 switch (wiz->master_lane_num[i]) { in wiz_phy_reset_deassert()
1281 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
1284 regmap_field_write(wiz->typec_ln23_swap, 1); in wiz_phy_reset_deassert()
1295 ret = regmap_field_write(wiz->phy_reset_n, true); in wiz_phy_reset_deassert()
1299 ret = wiz_phy_fullrt_div(wiz, id - 1); in wiz_phy_reset_deassert()
1303 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) in wiz_phy_reset_deassert()
1304 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); in wiz_phy_reset_deassert()
1306 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); in wiz_phy_reset_deassert()
1382 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1385 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1388 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1391 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1394 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data,
1397 .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data,
1407 serdes = of_get_child_by_name(dev->of_node, "serdes"); in wiz_get_lane_phy_types()
1409 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); in wiz_get_lane_phy_types()
1410 return -EINVAL; in wiz_get_lane_phy_types()
1426 __func__, subnode->name, ret); in wiz_get_lane_phy_types()
1429 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); in wiz_get_lane_phy_types()
1430 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); in wiz_get_lane_phy_types()
1432 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, in wiz_get_lane_phy_types()
1433 reg, reg + num_lanes - 1, phy_type); in wiz_get_lane_phy_types()
1436 wiz->master_lane_num[i] = reg; in wiz_get_lane_phy_types()
1437 wiz->lane_phy_type[i] = phy_type; in wiz_get_lane_phy_types()
1447 struct device *dev = &pdev->dev; in wiz_probe()
1448 struct device_node *node = dev->of_node; in wiz_probe()
1462 return -ENOMEM; in wiz_probe()
1467 return -EINVAL; in wiz_probe()
1470 wiz->data = data; in wiz_probe()
1471 wiz->type = data->type; in wiz_probe()
1476 return -ENODEV; in wiz_probe()
1487 ret = -ENOMEM; in wiz_probe()
1498 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); in wiz_probe()
1499 if (IS_ERR(wiz->scm_regmap)) { in wiz_probe()
1500 if (wiz->type == J7200_WIZ_10G) { in wiz_probe()
1502 ret = -ENODEV; in wiz_probe()
1506 wiz->scm_regmap = NULL; in wiz_probe()
1509 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in wiz_probe()
1511 dev_err(dev, "Failed to read num-lanes property\n"); in wiz_probe()
1517 ret = -ENODEV; in wiz_probe()
1521 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", in wiz_probe()
1523 if (IS_ERR(wiz->gpio_typec_dir)) { in wiz_probe()
1524 ret = PTR_ERR(wiz->gpio_typec_dir); in wiz_probe()
1525 if (ret != -EPROBE_DEFER) in wiz_probe()
1526 dev_err(dev, "Failed to request typec-dir gpio: %d\n", in wiz_probe()
1531 if (wiz->gpio_typec_dir) { in wiz_probe()
1532 ret = of_property_read_u32(node, "typec-dir-debounce-ms", in wiz_probe()
1533 &wiz->typec_dir_delay); in wiz_probe()
1534 if (ret && ret != -EINVAL) { in wiz_probe()
1535 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
1539 /* use min. debounce from Type-C spec if not provided in DT */ in wiz_probe()
1540 if (ret == -EINVAL) in wiz_probe()
1541 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; in wiz_probe()
1543 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || in wiz_probe()
1544 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { in wiz_probe()
1545 ret = -EINVAL; in wiz_probe()
1546 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
1555 wiz->dev = dev; in wiz_probe()
1556 wiz->regmap = regmap; in wiz_probe()
1557 wiz->num_lanes = num_lanes; in wiz_probe()
1558 wiz->clk_mux_sel = data->clk_mux_sel; in wiz_probe()
1559 wiz->clk_div_sel = clk_div_sel; in wiz_probe()
1560 wiz->clk_div_sel_num = data->clk_div_sel_num; in wiz_probe()
1571 if (wiz->scm_regmap) in wiz_probe()
1572 regmap_field_write(wiz->sup_legacy_clk_override, 1); in wiz_probe()
1574 phy_reset_dev = &wiz->wiz_phy_reset_dev; in wiz_probe()
1575 phy_reset_dev->dev = dev; in wiz_probe()
1576 phy_reset_dev->ops = &wiz_phy_reset_ops, in wiz_probe()
1577 phy_reset_dev->owner = THIS_MODULE, in wiz_probe()
1578 phy_reset_dev->of_node = node; in wiz_probe()
1580 phy_reset_dev->nr_resets = num_lanes + 1; in wiz_probe()
1601 for (i = 0; i < wiz->num_lanes; i++) { in wiz_probe()
1602 regmap_field_read(wiz->p_enable[i], &val); in wiz_probe()
1620 ret = -ENOMEM; in wiz_probe()
1623 wiz->serdes_pdev = serdes_pdev; in wiz_probe()
1643 struct device *dev = &pdev->dev; in wiz_remove()
1644 struct device_node *node = dev->of_node; in wiz_remove()
1649 serdes_pdev = wiz->serdes_pdev; in wiz_remove()
1651 of_platform_device_destroy(&serdes_pdev->dev, NULL); in wiz_remove()