43 	struct phy	*if_phy;  member
72 	struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);  in phy_gmii_sel_mode()  local
73 	const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;  in phy_gmii_sel_mode()
74 	struct device *dev = if_phy->priv->dev;  in phy_gmii_sel_mode()
106 		if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1))  in phy_gmii_sel_mode()
130 	if_phy->phy_if_mode = submode;  in phy_gmii_sel_mode()
133 		__func__, if_phy->id, submode, rgmii_id,  in phy_gmii_sel_mode()
134 		if_phy->rmii_clock_external);  in phy_gmii_sel_mode()
136 	regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];  in phy_gmii_sel_mode()
139 		dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);  in phy_gmii_sel_mode()
144 	    if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {  in phy_gmii_sel_mode()
145 		regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];  in phy_gmii_sel_mode()
152 	    if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {  in phy_gmii_sel_mode()
153 		regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];  in phy_gmii_sel_mode()
155 					 if_phy->rmii_clock_external);  in phy_gmii_sel_mode()
162 		 if_phy->id, phy_modes(submode));  in phy_gmii_sel_mode()
323 	return priv->if_phys[phy_id].if_phy;  in phy_gmii_sel_of_xlate()
327 			     struct phy_gmii_sel_phy_priv *if_phy)  in phy_gmii_init_phy()  argument
336 	if_phy->id = port;  in phy_gmii_init_phy()
337 	if_phy->priv = priv;  in phy_gmii_init_phy()
348 	if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield;  in phy_gmii_init_phy()
358 		if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield;  in phy_gmii_init_phy()
371 		if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield;  in phy_gmii_init_phy()
376 	if_phy->if_phy = devm_phy_create(dev,  in phy_gmii_init_phy()
379 	if (IS_ERR(if_phy->if_phy)) {  in phy_gmii_init_phy()
380 		ret = PTR_ERR(if_phy->if_phy);  in phy_gmii_init_phy()
384 	phy_set_drvdata(if_phy->if_phy, if_phy);  in phy_gmii_init_phy()