Lines Matching refs:XUSB_PADCTL_UPHY_PLL_P0_CTL2

184 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364  macro
486 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
491 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
504 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
506 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
546 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
548 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
553 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
565 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
567 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
572 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
652 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()
654 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in tegra210_pex_uphy_enable()