Lines Matching refs:value
468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
501 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
502 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
504 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
505 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
509 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
510 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
512 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
513 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_pex_uphy_enable()
517 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_pex_uphy_enable()
520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
523 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_pex_uphy_enable()
527 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_pex_uphy_enable()
529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
532 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_pex_uphy_enable()
533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
536 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_pex_uphy_enable()
538 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
542 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
543 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_pex_uphy_enable()
544 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
546 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
547 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
548 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
553 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
554 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_pex_uphy_enable()
565 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
566 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
567 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
572 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
573 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_pex_uphy_enable()
584 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
585 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_pex_uphy_enable()
586 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
591 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
592 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_pex_uphy_enable()
603 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
604 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_pex_uphy_enable()
606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
612 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_pex_uphy_enable()
623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
624 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_pex_uphy_enable()
625 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
630 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
631 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_pex_uphy_enable()
642 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
643 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_pex_uphy_enable()
644 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
648 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
649 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
650 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
652 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
653 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
654 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
656 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
657 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
658 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
668 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_enable()
669 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i); in tegra210_pex_uphy_enable()
670 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_enable()
685 u32 value; in tegra210_pex_uphy_disable() local
694 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_disable()
695 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i); in tegra210_pex_uphy_disable()
696 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_disable()
708 u32 value; in tegra210_sata_uphy_enable() local
732 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
733 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_sata_uphy_enable()
735 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_sata_uphy_enable()
737 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
739 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
740 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_sata_uphy_enable()
742 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_sata_uphy_enable()
744 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
746 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
747 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
748 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
750 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
751 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
752 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
754 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
755 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
756 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
758 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
759 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_sata_uphy_enable()
763 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; in tegra210_sata_uphy_enable()
766 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_sata_uphy_enable()
769 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << in tegra210_sata_uphy_enable()
772 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; in tegra210_sata_uphy_enable()
773 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
775 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
776 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_sata_uphy_enable()
782 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_sata_uphy_enable()
785 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << in tegra210_sata_uphy_enable()
788 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
790 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
791 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_sata_uphy_enable()
792 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
794 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
795 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_sata_uphy_enable()
797 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
801 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
802 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_sata_uphy_enable()
803 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
805 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
806 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
807 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
812 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
813 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_sata_uphy_enable()
824 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
825 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
826 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
831 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
832 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_sata_uphy_enable()
843 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
844 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_sata_uphy_enable()
845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
850 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
851 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_sata_uphy_enable()
862 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
863 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_sata_uphy_enable()
865 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
870 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
871 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_sata_uphy_enable()
882 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
883 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_sata_uphy_enable()
884 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
889 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
890 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_sata_uphy_enable()
901 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
902 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_sata_uphy_enable()
903 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
907 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
908 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
909 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
911 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
912 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
913 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
915 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
916 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
917 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
927 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_enable()
928 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i); in tegra210_sata_uphy_enable()
929 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_enable()
944 u32 value; in tegra210_sata_uphy_disable() local
953 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_disable()
954 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i); in tegra210_sata_uphy_disable()
955 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_disable()
963 u32 value; in tegra210_aux_mux_lp0_clamp_disable() local
965 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
966 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_aux_mux_lp0_clamp_disable()
967 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
971 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
972 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_aux_mux_lp0_clamp_disable()
973 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
977 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
978 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_aux_mux_lp0_clamp_disable()
979 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
984 u32 value; in tegra210_aux_mux_lp0_clamp_enable() local
986 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
987 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_aux_mux_lp0_clamp_enable()
988 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
992 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
993 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_aux_mux_lp0_clamp_enable()
994 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
998 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
999 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_aux_mux_lp0_clamp_enable()
1000 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
1036 u32 value; in tegra210_hsic_set_idle() local
1038 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
1040 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_set_idle()
1045 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
1049 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
1053 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
1064 u32 value; in tegra210_usb3_enable_phy_sleepwalk() local
1073 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1074 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port); in tegra210_usb3_enable_phy_sleepwalk()
1075 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port); in tegra210_usb3_enable_phy_sleepwalk()
1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1095 u32 value; in tegra210_usb3_disable_phy_sleepwalk() local
1104 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1105 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port); in tegra210_usb3_disable_phy_sleepwalk()
1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1111 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port); in tegra210_usb3_disable_phy_sleepwalk()
1112 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1124 u32 value; in tegra210_usb3_enable_phy_wake() local
1133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1134 value &= ~ALL_WAKE_EVENTS; in tegra210_usb3_enable_phy_wake()
1135 value |= SS_PORT_WAKEUP_EVENT(port); in tegra210_usb3_enable_phy_wake()
1136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1140 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1141 value &= ~ALL_WAKE_EVENTS; in tegra210_usb3_enable_phy_wake()
1142 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port); in tegra210_usb3_enable_phy_wake()
1143 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1155 u32 value; in tegra210_usb3_disable_phy_wake() local
1164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1165 value &= ~ALL_WAKE_EVENTS; in tegra210_usb3_disable_phy_wake()
1166 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port); in tegra210_usb3_disable_phy_wake()
1167 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1171 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1172 value &= ~ALL_WAKE_EVENTS; in tegra210_usb3_disable_phy_wake()
1173 value |= SS_PORT_WAKEUP_EVENT(port); in tegra210_usb3_disable_phy_wake()
1174 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1185 u32 value; in tegra210_usb3_phy_remote_wake_detected() local
1190 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_phy_remote_wake_detected()
1191 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index))) in tegra210_usb3_phy_remote_wake_detected()
1201 u32 value; in tegra210_utmi_enable_phy_wake() local
1205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1206 value &= ~ALL_WAKE_EVENTS; in tegra210_utmi_enable_phy_wake()
1207 value |= USB2_PORT_WAKEUP_EVENT(index); in tegra210_utmi_enable_phy_wake()
1208 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1212 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1213 value &= ~ALL_WAKE_EVENTS; in tegra210_utmi_enable_phy_wake()
1214 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra210_utmi_enable_phy_wake()
1215 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1226 u32 value; in tegra210_utmi_disable_phy_wake() local
1230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1231 value &= ~ALL_WAKE_EVENTS; in tegra210_utmi_disable_phy_wake()
1232 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra210_utmi_disable_phy_wake()
1233 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1237 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1238 value &= ~ALL_WAKE_EVENTS; in tegra210_utmi_disable_phy_wake()
1239 value |= USB2_PORT_WAKEUP_EVENT(index); in tegra210_utmi_disable_phy_wake()
1240 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1251 u32 value; in tegra210_utmi_phy_remote_wake_detected() local
1253 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_phy_remote_wake_detected()
1254 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) && in tegra210_utmi_phy_remote_wake_detected()
1255 (value & USB2_PORT_WAKEUP_EVENT(index))) in tegra210_utmi_phy_remote_wake_detected()
1265 u32 value; in tegra210_hsic_enable_phy_wake() local
1269 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1270 value &= ~ALL_WAKE_EVENTS; in tegra210_hsic_enable_phy_wake()
1271 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index); in tegra210_hsic_enable_phy_wake()
1272 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1276 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1277 value &= ~ALL_WAKE_EVENTS; in tegra210_hsic_enable_phy_wake()
1278 value |= USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra210_hsic_enable_phy_wake()
1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1290 u32 value; in tegra210_hsic_disable_phy_wake() local
1294 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1295 value &= ~ALL_WAKE_EVENTS; in tegra210_hsic_disable_phy_wake()
1296 value &= ~USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra210_hsic_disable_phy_wake()
1297 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1301 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1302 value &= ~ALL_WAKE_EVENTS; in tegra210_hsic_disable_phy_wake()
1303 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index); in tegra210_hsic_disable_phy_wake()
1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1315 u32 value; in tegra210_hsic_phy_remote_wake_detected() local
1317 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_phy_remote_wake_detected()
1318 if ((value & USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index)) && in tegra210_hsic_phy_remote_wake_detected()
1319 (value & USB2_HSIC_PORT_WAKEUP_EVENT(index))) in tegra210_hsic_phy_remote_wake_detected()
1327 u32 value; \
1328 WARN(regmap_read(_priv->regmap, _offset, &value), "read %s failed\n", #_offset);\
1329 value; \
1341 u32 value, tctrl, pctrl, rpd_ctrl; in tegra210_pmc_utmi_enable_phy_sleepwalk() local
1349 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1350 tctrl = TCTRL_VALUE(value); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1351 pctrl = PCTRL_VALUE(value); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1353 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1354 rpd_ctrl = RPD_CTRL_VALUE(value); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1357 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1358 value &= ~UTMIP_MASTER_ENABLE(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1359 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1362 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1363 value |= UTMIP_PWR(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1364 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1367 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1368 value &= ~UTMIP_LINE_DEB_CNT(~0); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1369 value |= UTMIP_LINE_DEB_CNT(0x1); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1370 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1373 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1374 value &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) | in tegra210_pmc_utmi_enable_phy_sleepwalk()
1376 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_FAKE(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1379 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1380 value &= ~UTMIP_LINE_WAKEUP_EN(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1381 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1384 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1385 value &= ~UTMIP_WAKE_VAL(port, ~0); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1386 value |= UTMIP_WAKE_VAL_NONE(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1387 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1390 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1391 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1392 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1395 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1396 value &= ~SPEED(port, ~0); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1400 value |= UTMI_HS(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1404 value |= UTMI_FS(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1408 value |= UTMI_LS(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1412 value |= UTMI_RST(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1416 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SAVED_STATE(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1419 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1420 value |= UTMIP_LINEVAL_WALK_EN(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1421 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1427 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1428 value |= UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) | UTMIP_CAP_CFG(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1429 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1432 value = padctl_pmc_readl(priv, PMC_UTMIP_TERM_PAD_CFG); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1433 value &= ~(TCTRL_VAL(~0) | PCTRL_VAL(~0)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1434 value |= (TCTRL_VAL(tctrl) | PCTRL_VAL(pctrl)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1435 padctl_pmc_writel(priv, value, PMC_UTMIP_TERM_PAD_CFG); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1437 value = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1438 value &= ~RPD_CTRL_PX(~0); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1439 value |= RPD_CTRL_PX(rpd_ctrl); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1440 padctl_pmc_writel(priv, value, PMC_UTMIP_PAD_CFGX(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1447 value = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1448 value = UTMIP_USBOP_RPD_A | UTMIP_USBOP_RPD_B | UTMIP_USBOP_RPD_C | UTMIP_USBOP_RPD_D; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1449 value |= UTMIP_USBON_RPD_A | UTMIP_USBON_RPD_B | UTMIP_USBON_RPD_C | UTMIP_USBON_RPD_D; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1455 value |= UTMIP_HIGHZ_A; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1456 value |= UTMIP_AP_A; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1457 value |= UTMIP_AN_B | UTMIP_AN_C | UTMIP_AN_D; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1462 value |= UTMIP_HIGHZ_A; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1463 value |= UTMIP_AN_A; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1464 value |= UTMIP_AP_B | UTMIP_AP_C | UTMIP_AP_D; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1468 value |= UTMIP_HIGHZ_A | UTMIP_HIGHZ_B | UTMIP_HIGHZ_C | UTMIP_HIGHZ_D; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1472 padctl_pmc_writel(priv, value, PMC_UTMIP_SLEEPWALK_PX(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1475 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1476 value &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1477 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1482 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1483 value |= UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | UTMIP_TCTRL_USE_PMC(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1484 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1486 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1487 value |= UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1488 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1491 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1492 value &= ~UTMIP_WAKE_VAL(port, ~0); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1493 value |= UTMIP_WAKE_VAL_ANY(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1494 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1497 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1498 value |= UTMIP_MASTER_ENABLE(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1499 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1501 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1502 value |= UTMIP_LINE_WAKEUP_EN(port); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1503 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1513 u32 value; in tegra210_pmc_utmi_disable_phy_sleepwalk() local
1519 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1520 value &= ~UTMIP_MASTER_ENABLE(port); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1521 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1523 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1524 value &= ~UTMIP_LINE_WAKEUP_EN(port); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1525 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1528 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1529 value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | in tegra210_pmc_utmi_disable_phy_sleepwalk()
1531 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1533 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1534 value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1535 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1538 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1539 value &= ~UTMIP_WAKE_VAL(port, ~0); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1540 value |= UTMIP_WAKE_VAL_NONE(port); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1541 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1544 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1545 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port)); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1546 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1549 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1550 value |= UTMIP_CLR_WAKE_ALARM(port); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1551 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1561 u32 value; in tegra210_pmc_hsic_enable_phy_sleepwalk() local
1567 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1568 value &= ~UHSIC_MASTER_ENABLE; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1569 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1572 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1573 value |= UHSIC_PWR; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1574 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1577 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1578 value &= ~UHSIC_LINE_DEB_CNT(~0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1579 value |= UHSIC_LINE_DEB_CNT(0x1); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1580 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1583 value = padctl_pmc_readl(priv, PMC_UHSIC_FAKE); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1584 value &= ~(UHSIC_FAKE_STROBE_VAL | UHSIC_FAKE_DATA_VAL | in tegra210_pmc_hsic_enable_phy_sleepwalk()
1586 padctl_pmc_writel(priv, value, PMC_UHSIC_FAKE); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1589 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1590 value &= ~UHSIC_LINE_WAKEUP_EN; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1591 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1594 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1595 value &= ~UHSIC_WAKE_VAL(~0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1596 value |= UHSIC_WAKE_VAL_NONE; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1597 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1600 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1601 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1602 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1605 value = padctl_pmc_readl(priv, PMC_UHSIC_SAVED_STATE); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1606 value &= ~UHSIC_MODE(~0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1607 value |= UHSIC_HS; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1608 padctl_pmc_writel(priv, value, PMC_UHSIC_SAVED_STATE); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1611 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1612 value |= UHSIC_WAKE_WALK_EN | UHSIC_LINEVAL_WALK_EN; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1613 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1619 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1620 value |= UHSIC_CLR_WALK_PTR | UHSIC_CLR_WAKE_ALARM; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1621 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1628 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_P0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1629 value = UHSIC_DATA0_RPD_A | UHSIC_DATA0_RPU_B | UHSIC_DATA0_RPU_C | UHSIC_DATA0_RPU_D | in tegra210_pmc_hsic_enable_phy_sleepwalk()
1631 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_P0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1634 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1635 value &= ~(STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1636 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1641 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1642 value &= ~UHSIC_WAKE_VAL(~0); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1643 value |= UHSIC_WAKE_VAL_SD10; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1644 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1647 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1648 value |= UHSIC_MASTER_ENABLE; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1649 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1651 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1652 value |= UHSIC_LINE_WAKEUP_EN; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1653 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1662 u32 value; in tegra210_pmc_hsic_disable_phy_sleepwalk() local
1668 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1669 value &= ~UHSIC_MASTER_ENABLE; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1670 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1672 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1673 value &= ~UHSIC_LINE_WAKEUP_EN; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1674 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1677 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1678 value &= ~UHSIC_WAKE_VAL(~0); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1679 value |= UHSIC_WAKE_VAL_NONE; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1680 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1683 value = padctl_pmc_readl(priv, PMC_USB_AO); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1684 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1685 padctl_pmc_writel(priv, value, PMC_USB_AO); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1688 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1689 value |= UHSIC_CLR_WAKE_ALARM; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1690 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1700 u32 value, offset; in tegra210_usb3_set_lfps_detect() local
1713 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
1715 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << in tegra210_usb3_set_lfps_detect()
1721 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << in tegra210_usb3_set_lfps_detect()
1727 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
1805 u32 value; in tegra210_usb2_phy_init() local
1821 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
1822 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << in tegra210_usb2_phy_init()
1824 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << in tegra210_usb2_phy_init()
1826 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
1858 u32 value; in tegra210_xusb_padctl_vbus_override() local
1862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
1865 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_vbus_override()
1866 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_vbus_override()
1868 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << in tegra210_xusb_padctl_vbus_override()
1871 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_vbus_override()
1874 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
1882 u32 value; in tegra210_xusb_padctl_id_override() local
1886 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1889 if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) { in tegra210_xusb_padctl_id_override()
1890 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; in tegra210_xusb_padctl_id_override()
1891 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1894 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1897 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_id_override()
1899 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED << in tegra210_xusb_padctl_id_override()
1902 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << in tegra210_xusb_padctl_id_override()
1904 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << in tegra210_xusb_padctl_id_override()
1908 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1961 u32 value; in tegra210_usb2_phy_power_on() local
1975 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1976 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK( in tegra210_usb2_phy_power_on()
1978 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP( in tegra210_usb2_phy_power_on()
1980 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1982 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1983 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN( in tegra210_usb2_phy_power_on()
1985 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1989 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1990 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY( in tegra210_usb2_phy_power_on()
1992 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1996 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1997 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN( in tegra210_usb2_phy_power_on()
1999 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
2002 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2003 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << in tegra210_usb2_phy_power_on()
2007 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << in tegra210_usb2_phy_power_on()
2011 value |= in tegra210_usb2_phy_power_on()
2015 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2017 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
2018 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); in tegra210_usb2_phy_power_on()
2020 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index); in tegra210_usb2_phy_power_on()
2022 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index); in tegra210_usb2_phy_power_on()
2024 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); in tegra210_usb2_phy_power_on()
2026 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index); in tegra210_usb2_phy_power_on()
2027 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
2029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
2030 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << in tegra210_usb2_phy_power_on()
2035 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
2038 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
2040 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
2041 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << in tegra210_usb2_phy_power_on()
2048 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
2052 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
2054 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
2056 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << in tegra210_usb2_phy_power_on()
2059 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; in tegra210_usb2_phy_power_on()
2061 value |= in tegra210_usb2_phy_power_on()
2064 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
2077 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2078 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << in tegra210_usb2_phy_power_on()
2082 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << in tegra210_usb2_phy_power_on()
2086 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2088 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2089 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_on()
2090 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2094 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2095 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; in tegra210_usb2_phy_power_on()
2096 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2118 u32 value; in tegra210_usb2_phy_power_off() local
2130 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2131 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY( in tegra210_usb2_phy_power_off()
2133 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2138 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN( in tegra210_usb2_phy_power_off()
2140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2145 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN( in tegra210_usb2_phy_power_off()
2147 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2149 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
2150 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake, in tegra210_usb2_phy_power_off()
2152 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
2161 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
2162 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_off()
2163 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
2298 u32 value; in tegra210_hsic_phy_init() local
2300 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
2301 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << in tegra210_hsic_phy_init()
2303 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << in tegra210_hsic_phy_init()
2305 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
2322 u32 value; in tegra210_hsic_phy_power_on() local
2332 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
2333 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << in tegra210_hsic_phy_power_on()
2335 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
2337 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
2339 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
2340 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << in tegra210_hsic_phy_power_on()
2344 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
2348 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
2350 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
2351 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_phy_power_on()
2363 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_phy_power_on()
2366 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
2372 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2373 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << in tegra210_hsic_phy_power_on()
2377 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << in tegra210_hsic_phy_power_on()
2381 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2385 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2386 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; in tegra210_hsic_phy_power_on()
2387 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2406 u32 value; in tegra210_hsic_phy_power_off() local
2408 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
2409 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | in tegra210_hsic_phy_power_off()
2418 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
2499 u32 value; in tegra210_uphy_lane_iddq_enable() local
2501 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_enable()
2502 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD; in tegra210_uphy_lane_iddq_enable()
2503 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD; in tegra210_uphy_lane_iddq_enable()
2504 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD; in tegra210_uphy_lane_iddq_enable()
2505 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD; in tegra210_uphy_lane_iddq_enable()
2506 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ; in tegra210_uphy_lane_iddq_enable()
2507 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK; in tegra210_uphy_lane_iddq_enable()
2508 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL; in tegra210_uphy_lane_iddq_enable()
2509 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ; in tegra210_uphy_lane_iddq_enable()
2510 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK; in tegra210_uphy_lane_iddq_enable()
2511 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL; in tegra210_uphy_lane_iddq_enable()
2512 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_enable()
2518 u32 value; in tegra210_uphy_lane_iddq_disable() local
2520 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_disable()
2521 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD; in tegra210_uphy_lane_iddq_disable()
2522 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD; in tegra210_uphy_lane_iddq_disable()
2523 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD; in tegra210_uphy_lane_iddq_disable()
2524 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD; in tegra210_uphy_lane_iddq_disable()
2525 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ; in tegra210_uphy_lane_iddq_disable()
2526 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK; in tegra210_uphy_lane_iddq_disable()
2527 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL; in tegra210_uphy_lane_iddq_disable()
2528 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ; in tegra210_uphy_lane_iddq_disable()
2529 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK; in tegra210_uphy_lane_iddq_disable()
2530 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL; in tegra210_uphy_lane_iddq_disable()
2531 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_disable()
2584 u32 value; in tegra210_usb3_phy_power_on() local
2593 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_phy_power_on()
2596 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_phy_power_on()
2598 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_phy_power_on()
2600 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_phy_power_on()
2601 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_phy_power_on()
2602 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_phy_power_on()
2604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_phy_power_on()
2605 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << in tegra210_usb3_phy_power_on()
2607 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << in tegra210_usb3_phy_power_on()
2609 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_phy_power_on()
2611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_phy_power_on()
2612 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << in tegra210_usb3_phy_power_on()
2614 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << in tegra210_usb3_phy_power_on()
2616 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_phy_power_on()
2621 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_phy_power_on()
2622 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << in tegra210_usb3_phy_power_on()
2624 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << in tegra210_usb3_phy_power_on()
2626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_phy_power_on()
2631 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2632 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_phy_power_on()
2633 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2637 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2638 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_phy_power_on()
2639 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2643 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2644 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_phy_power_on()
2645 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2657 u32 value; in tegra210_usb3_phy_power_off() local
2666 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2667 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_phy_power_off()
2668 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2672 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2673 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_phy_power_off()
2674 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2678 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2679 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_phy_power_off()
2680 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
3090 u32 value; in tegra210_utmi_port_reset() local
3095 value = padctl_readl(padctl, in tegra210_utmi_port_reset()
3098 if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) || in tegra210_utmi_port_reset()
3099 (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) { in tegra210_utmi_port_reset()
3112 u32 value; in tegra210_xusb_read_fuse_calibration() local
3115 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); in tegra210_xusb_read_fuse_calibration()
3121 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & in tegra210_xusb_read_fuse_calibration()
3126 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & in tegra210_xusb_read_fuse_calibration()
3129 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); in tegra210_xusb_read_fuse_calibration()
3134 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & in tegra210_xusb_read_fuse_calibration()