206 	void __iomem *pipebase;  member
939 		|| (!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_pcie()
966 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */  in miphy28lp_init_pcie()
967 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */  in miphy28lp_init_pcie()
968 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */  in miphy28lp_init_pcie()
969 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */  in miphy28lp_init_pcie()
970 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */  in miphy28lp_init_pcie()
971 	writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */  in miphy28lp_init_pcie()
982 	if ((!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_usb3()
998 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);  in miphy28lp_init_usb3()
999 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);  in miphy28lp_init_usb3()
1000 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);  in miphy28lp_init_usb3()
1001 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);  in miphy28lp_init_usb3()
1002 	writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);  in miphy28lp_init_usb3()
1003 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);  in miphy28lp_init_usb3()
1006 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);  in miphy28lp_init_usb3()
1007 	writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);  in miphy28lp_init_usb3()
1008 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);  in miphy28lp_init_usb3()
1009 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);  in miphy28lp_init_usb3()
1010 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);  in miphy28lp_init_usb3()
1011 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);  in miphy28lp_init_usb3()
1012 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);  in miphy28lp_init_usb3()
1013 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);  in miphy28lp_init_usb3()
1068 					     &miphy_phy->pipebase);  in miphy28lp_get_addr()