Lines Matching +full:ext +full:- +full:gen
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
238 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
367 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
378 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
379 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
391 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
396 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
399 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
400 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
401 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); in miphy28lp_pll_calibration()
402 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); in miphy28lp_pll_calibration()
403 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); in miphy28lp_pll_calibration()
412 if (miphy_phy->type != PHY_TYPE_SATA) in miphy28lp_pll_calibration()
417 if (miphy_phy->type == PHY_TYPE_USB3) { in miphy28lp_pll_calibration()
432 void __iomem *base = miphy_phy->base; in miphy28lp_sata_config_gen()
436 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i]; in miphy28lp_sata_config_gen() local
439 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_sata_config_gen()
440 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_sata_config_gen()
441 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_sata_config_gen()
442 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_sata_config_gen()
445 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_sata_config_gen()
446 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_sata_config_gen()
449 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_sata_config_gen()
450 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_sata_config_gen()
451 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_sata_config_gen()
452 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_sata_config_gen()
453 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); in miphy28lp_sata_config_gen()
459 void __iomem *base = miphy_phy->base; in miphy28lp_pcie_config_gen()
463 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i]; in miphy28lp_pcie_config_gen() local
466 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_pcie_config_gen()
467 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_pcie_config_gen()
468 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_pcie_config_gen()
469 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_pcie_config_gen()
472 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); in miphy28lp_pcie_config_gen()
473 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_pcie_config_gen()
474 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_pcie_config_gen()
476 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); in miphy28lp_pcie_config_gen()
479 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_pcie_config_gen()
480 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_pcie_config_gen()
481 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_pcie_config_gen()
482 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_pcie_config_gen()
491 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6, in miphy28lp_wait_compensation()
499 void __iomem *base = miphy_phy->base; in miphy28lp_compensation()
506 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_compensation()
509 if (miphy_phy->type == PHY_TYPE_PCIE) in miphy28lp_compensation()
516 /* TX compensation offset to re-center TX impedance */ in miphy28lp_compensation()
519 if (miphy_phy->type == PHY_TYPE_PCIE) in miphy28lp_compensation()
527 void __iomem *base = miphy_phy->base; in miphy28_usb3_miphy_reset()
555 void __iomem *base = miphy_phy->base; in miphy_sata_tune_ssc()
593 void __iomem *base = miphy_phy->base; in miphy_pcie_tune_ssc()
634 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); in miphy_tune_tx_impedance()
639 void __iomem *base = miphy_phy->base; in miphy28lp_configure_sata()
665 if (miphy_phy->px_rx_pol_inv) { in miphy28lp_configure_sata()
667 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
669 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
672 if (miphy_phy->ssc) in miphy28lp_configure_sata()
675 if (miphy_phy->tx_impedance) in miphy28lp_configure_sata()
683 void __iomem *base = miphy_phy->base; in miphy28lp_configure_pcie()
708 if (miphy_phy->ssc) in miphy28lp_configure_pcie()
711 if (miphy_phy->tx_impedance) in miphy28lp_configure_pcie()
720 void __iomem *base = miphy_phy->base; in miphy28lp_configure_usb3()
751 /* TX compensation offset to re-center TX impedance */ in miphy28lp_configure_usb3()
808 if (miphy_phy->type == PHY_TYPE_SATA) in miphy_is_ready()
811 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1, in miphy_is_ready()
818 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy_osc_is_ready()
821 if (!miphy_phy->osc_rdy) in miphy_osc_is_ready()
824 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) in miphy_osc_is_ready()
825 return -EINVAL; in miphy_osc_is_ready()
827 return regmap_read_poll_timeout(miphy_dev->regmap, in miphy_osc_is_ready()
828 miphy_phy->syscfg_reg[SYSCFG_STATUS], in miphy_osc_is_ready()
838 index = of_property_match_string(child, "reg-names", rname); in miphy28lp_get_resource_byname()
840 return -ENODEV; in miphy28lp_get_resource_byname()
858 return -ENOENT; in miphy28lp_get_one_addr()
869 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_setup()
871 if (!miphy_phy->syscfg_reg[SYSCFG_CTRL]) in miphy28lp_setup()
872 return -EINVAL; in miphy28lp_setup()
874 err = reset_control_assert(miphy_phy->miphy_rst); in miphy28lp_setup()
876 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_setup()
880 if (miphy_phy->osc_force_ext) in miphy28lp_setup()
883 regmap_update_bits(miphy_dev->regmap, in miphy28lp_setup()
884 miphy_phy->syscfg_reg[SYSCFG_CTRL], in miphy28lp_setup()
887 err = reset_control_deassert(miphy_phy->miphy_rst); in miphy28lp_setup()
889 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_setup()
898 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_sata()
901 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || in miphy28lp_init_sata()
902 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) || in miphy28lp_init_sata()
903 (!miphy_phy->base)) in miphy28lp_init_sata()
904 return -EINVAL; in miphy28lp_init_sata()
906 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_sata()
908 /* Configure the glue-logic */ in miphy28lp_init_sata()
909 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); in miphy28lp_init_sata()
911 regmap_update_bits(miphy_dev->regmap, in miphy28lp_init_sata()
912 miphy_phy->syscfg_reg[SYSCFG_SATA], in miphy28lp_init_sata()
915 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], in miphy28lp_init_sata()
922 dev_err(miphy_dev->dev, "SATA phy setup failed\n"); in miphy28lp_init_sata()
934 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_pcie()
937 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || in miphy28lp_init_pcie()
938 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) in miphy28lp_init_pcie()
939 || (!miphy_phy->base) || (!miphy_phy->pipebase)) in miphy28lp_init_pcie()
940 return -EINVAL; in miphy28lp_init_pcie()
942 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_pcie()
944 /* Configure the glue-logic */ in miphy28lp_init_pcie()
945 regmap_update_bits(miphy_dev->regmap, in miphy28lp_init_pcie()
946 miphy_phy->syscfg_reg[SYSCFG_SATA], in miphy28lp_init_pcie()
949 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], in miphy28lp_init_pcie()
956 dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); in miphy28lp_init_pcie()
966 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ in miphy28lp_init_pcie()
967 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ in miphy28lp_init_pcie()
968 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ in miphy28lp_init_pcie()
969 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ in miphy28lp_init_pcie()
970 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ in miphy28lp_init_pcie()
971 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ in miphy28lp_init_pcie()
979 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_usb3()
982 if ((!miphy_phy->base) || (!miphy_phy->pipebase)) in miphy28lp_init_usb3()
983 return -EINVAL; in miphy28lp_init_usb3()
985 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_usb3()
990 dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); in miphy28lp_init_usb3()
998 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); in miphy28lp_init_usb3()
999 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); in miphy28lp_init_usb3()
1000 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); in miphy28lp_init_usb3()
1001 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); in miphy28lp_init_usb3()
1002 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); in miphy28lp_init_usb3()
1003 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); in miphy28lp_init_usb3()
1005 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ in miphy28lp_init_usb3()
1006 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); in miphy28lp_init_usb3()
1007 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); in miphy28lp_init_usb3()
1008 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); in miphy28lp_init_usb3()
1009 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); in miphy28lp_init_usb3()
1010 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); in miphy28lp_init_usb3()
1011 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); in miphy28lp_init_usb3()
1012 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); in miphy28lp_init_usb3()
1013 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); in miphy28lp_init_usb3()
1021 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init()
1024 mutex_lock(&miphy_dev->miphy_mutex); in miphy28lp_init()
1026 switch (miphy_phy->type) { in miphy28lp_init()
1038 ret = -EINVAL; in miphy28lp_init()
1042 mutex_unlock(&miphy_dev->miphy_mutex); in miphy28lp_init()
1049 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_get_addr()
1050 struct device_node *phynode = miphy_phy->phy->dev.of_node; in miphy28lp_get_addr()
1053 if ((miphy_phy->type != PHY_TYPE_SATA) && in miphy28lp_get_addr()
1054 (miphy_phy->type != PHY_TYPE_PCIE) && in miphy28lp_get_addr()
1055 (miphy_phy->type != PHY_TYPE_USB3)) { in miphy28lp_get_addr()
1056 return -EINVAL; in miphy28lp_get_addr()
1059 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, in miphy28lp_get_addr()
1060 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA], in miphy28lp_get_addr()
1061 &miphy_phy->base); in miphy28lp_get_addr()
1065 if ((miphy_phy->type == PHY_TYPE_PCIE) || in miphy28lp_get_addr()
1066 (miphy_phy->type == PHY_TYPE_USB3)) { in miphy28lp_get_addr()
1067 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", in miphy28lp_get_addr()
1068 &miphy_phy->pipebase); in miphy28lp_get_addr()
1081 struct device_node *phynode = args->np; in miphy28lp_xlate()
1084 if (args->args_count != 1) { in miphy28lp_xlate()
1086 return ERR_PTR(-EINVAL); in miphy28lp_xlate()
1089 for (index = 0; index < miphy_dev->nphys; index++) in miphy28lp_xlate()
1090 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { in miphy28lp_xlate()
1091 miphy_phy = miphy_dev->phys[index]; in miphy28lp_xlate()
1097 return ERR_PTR(-EINVAL); in miphy28lp_xlate()
1100 miphy_phy->type = args->args[0]; in miphy28lp_xlate()
1106 return miphy_phy->phy; in miphy28lp_xlate()
1117 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_probe_resets()
1120 miphy_phy->miphy_rst = in miphy28lp_probe_resets()
1121 of_reset_control_get_shared(node, "miphy-sw-rst"); in miphy28lp_probe_resets()
1123 if (IS_ERR(miphy_phy->miphy_rst)) { in miphy28lp_probe_resets()
1124 dev_err(miphy_dev->dev, in miphy28lp_probe_resets()
1126 return PTR_ERR(miphy_phy->miphy_rst); in miphy28lp_probe_resets()
1129 err = reset_control_deassert(miphy_phy->miphy_rst); in miphy28lp_probe_resets()
1131 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_probe_resets()
1144 miphy_phy->osc_force_ext = in miphy28lp_of_probe()
1145 of_property_read_bool(np, "st,osc-force-ext"); in miphy28lp_of_probe()
1147 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); in miphy28lp_of_probe()
1149 miphy_phy->px_rx_pol_inv = in miphy28lp_of_probe()
1152 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); in miphy28lp_of_probe()
1154 miphy_phy->tx_impedance = in miphy28lp_of_probe()
1155 of_property_read_bool(np, "st,tx-impedance-comp"); in miphy28lp_of_probe()
1157 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); in miphy28lp_of_probe()
1158 if (!miphy_phy->sata_gen) in miphy28lp_of_probe()
1159 miphy_phy->sata_gen = SATA_GEN1; in miphy28lp_of_probe()
1163 miphy_phy->syscfg_reg[i] = ctrlreg; in miphy28lp_of_probe()
1171 struct device_node *child, *np = pdev->dev.of_node; in miphy28lp_probe()
1177 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); in miphy28lp_probe()
1179 return -ENOMEM; in miphy28lp_probe()
1181 miphy_dev->nphys = of_get_child_count(np); in miphy28lp_probe()
1182 miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys, in miphy28lp_probe()
1183 sizeof(*miphy_dev->phys), GFP_KERNEL); in miphy28lp_probe()
1184 if (!miphy_dev->phys) in miphy28lp_probe()
1185 return -ENOMEM; in miphy28lp_probe()
1187 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in miphy28lp_probe()
1188 if (IS_ERR(miphy_dev->regmap)) { in miphy28lp_probe()
1189 dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); in miphy28lp_probe()
1190 return PTR_ERR(miphy_dev->regmap); in miphy28lp_probe()
1193 miphy_dev->dev = &pdev->dev; in miphy28lp_probe()
1195 dev_set_drvdata(&pdev->dev, miphy_dev); in miphy28lp_probe()
1197 mutex_init(&miphy_dev->miphy_mutex); in miphy28lp_probe()
1202 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), in miphy28lp_probe()
1205 ret = -ENOMEM; in miphy28lp_probe()
1209 miphy_dev->phys[port] = miphy_phy; in miphy28lp_probe()
1211 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops); in miphy28lp_probe()
1213 dev_err(&pdev->dev, "failed to create PHY\n"); in miphy28lp_probe()
1218 miphy_dev->phys[port]->phy = phy; in miphy28lp_probe()
1219 miphy_dev->phys[port]->phydev = miphy_dev; in miphy28lp_probe()
1225 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); in miphy28lp_probe()
1229 phy_set_drvdata(phy, miphy_dev->phys[port]); in miphy28lp_probe()
1234 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); in miphy28lp_probe()
1242 {.compatible = "st,miphy28lp-phy", },
1251 .name = "miphy28lp-phy",