phy/rockchip/phy-rockchip-inno-hdmi.c

23 #define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))  macro
36 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x)		UPDATE(x, 6, 0)
38 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x)		UPDATE(x, 7, 0)
53 #define RK3228_PRE_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
55 #define RK3228_PCLK_VCO_DIV_5(x)			UPDATE(x, 5, 5)
57 #define RK3228_PRE_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
59 #define RK3228_PRE_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
63 #define RK3228_PRE_PLL_PCLK_DIV_B(x)			UPDATE(x, 6, 5)
65 #define RK3228_PRE_PLL_PCLK_DIV_A(x)			UPDATE(x, 4, 0)
68 #define RK3228_PRE_PLL_PCLK_DIV_C(x)			UPDATE(x, 6, 5)
70 #define RK3228_PRE_PLL_PCLK_DIV_D(x)			UPDATE(x, 4, 0)
73 #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x)			UPDATE(x, 5, 4)
75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x)			UPDATE(x, 3, 2)
77 #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x)			UPDATE(x, 1, 0)
81 #define RK3228_POST_PLL_POST_DIV_ENABLE			UPDATE(3, 7, 6)
83 #define RK3228_POST_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
85 #define RK3228_POST_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
88 #define RK3228_POST_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
90 #define RK3228_POST_PLL_POST_DIV(x)			UPDATE(x, 5, 4)
95 #define RK3228_TMDS_CLK_CH_TA(x)			UPDATE(x, 7, 6)
96 #define RK3228_TMDS_DATA_CH2_TA(x)			UPDATE(x, 5, 4)
97 #define RK3228_TMDS_DATA_CH1_TA(x)			UPDATE(x, 3, 2)
98 #define RK3228_TMDS_DATA_CH0_TA(x)			UPDATE(x, 1, 0)
101 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x)		UPDATE(x, 5, 4)
103 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x)		UPDATE(x, 3, 2)
105 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x)		UPDATE(x, 1, 0)
107 #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x)		UPDATE(x, 7, 4)
108 #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x)		UPDATE(x, 3, 0)
110 #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x)		UPDATE(x, 7, 4)
111 #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x)		UPDATE(x, 3, 0)
122 #define RK3328_INT_TMDS_CLK(x)				UPDATE(x, 7, 4)
123 #define RK3328_INT_TMDS_D2(x)				UPDATE(x, 3, 0)
125 #define RK3328_INT_TMDS_D1(x)				UPDATE(x, 7, 4)
126 #define RK3328_INT_TMDS_D0(x)				UPDATE(x, 3, 0)
134 #define RK3328_PCLK_VCO_DIV_5(x)			UPDATE(x, 1, 1)
138 #define RK3328_PRE_PLL_PRE_DIV(x)			UPDATE(x, 5, 0)
143 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE			UPDATE(3, 5, 4)
145 #define RK3328_PRE_PLL_FB_DIV_11_8(x)			UPDATE((x) >> 8, 3, 0)
147 #define RK3328_PRE_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
150 #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)			UPDATE(x, 1, 0)
152 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)			UPDATE(x, 3, 2)
154 #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)			UPDATE(x, 5, 4)
158 #define RK3328_PRE_PLL_PCLK_DIV_B(x)			UPDATE(x, 6, 5)
160 #define RK3328_PRE_PLL_PCLK_DIV_A(x)			UPDATE(x, 4, 0)
164 #define RK3328_PRE_PLL_PCLK_DIV_C(x)			UPDATE(x, 6, 5)
166 #define RK3328_PRE_PLL_PCLK_DIV_D(x)			UPDATE(x, 4, 0)
174 #define RK3328_POST_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
175 #define RK3328_POST_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
177 #define RK3328_POST_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
198 #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x)	UPDATE((x) >> 8, 6, 0)
200 #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x)		UPDATE(x, 7, 0)
202 #define RK3328_TERM_RESISTOR_50				UPDATE(0, 2, 1)
203 #define RK3328_TERM_RESISTOR_62_5			UPDATE(1, 2, 1)
204 #define RK3328_TERM_RESISTOR_75				UPDATE(2, 2, 1)
205 #define RK3328_TERM_RESISTOR_100			UPDATE(3, 2, 1)
221 #define RK3328_PRE_PLL_FRAC_DIV_23_16(x)		UPDATE((x) >> 16, 7, 0)
223 #define RK3328_PRE_PLL_FRAC_DIV_15_8(x)			UPDATE((x) >> 8, 7, 0)
225 #define RK3328_PRE_PLL_FRAC_DIV_7_0(x)			UPDATE(x, 7, 0)