Lines Matching +full:tx +full:- +full:pcs
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
32 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
33 #include "phy-qcom-qmp-pcie-qhp.h"
73 /* set of registers with offsets different per-PHY */
75 /* PCS registers */
2152 u16 pcs; member
2154 u16 tx; member
2164 const struct qmp_phy_init_tbl *tx; member
2168 const struct qmp_phy_init_tbl *pcs; member
2176 /* struct qmp_phy_cfg - per-PHY initialization config */
2182 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
2226 void __iomem *pcs; member
2228 void __iomem *tx; member
2281 "vdda-phy", "vdda-pll",
2285 "vdda-phy", "vdda-pll", "vdda-qref",
2299 .pcs = 0x1800,
2300 .tx = 0x0800,
2306 .pcs = 0x0800,
2307 .tx = 0x0200,
2313 .pcs = 0x0800,
2315 .tx = 0x0200,
2321 .pcs = 0x0800,
2323 .tx = 0x0200,
2329 .pcs = 0x0a00,
2331 .tx = 0x0200,
2339 .pcs = 0x1200,
2341 .tx = 0x0000,
2349 .pcs = 0x0200,
2351 .tx = 0x0e00,
2359 .pcs = 0x1200,
2361 .tx = 0x0000,
2369 .pcs = 0x2200,
2371 .tx = 0x0,
2379 .pcs = 0x1200,
2381 .tx = 0x0000,
2396 .tx = ipq8074_pcie_tx_tbl,
2400 .pcs = ipq8074_pcie_pcs_tbl,
2421 .tx = ipq8074_pcie_gen3_tx_tbl,
2425 .pcs = ipq8074_pcie_gen3_pcs_tbl,
2450 .tx = ipq6018_pcie_tx_tbl,
2454 .pcs = ipq6018_pcie_pcs_tbl,
2477 .tx = sdm845_qmp_pcie_tx_tbl,
2481 .pcs = sdm845_qmp_pcie_pcs_tbl,
2504 .tx = sdm845_qhp_pcie_tx_tbl,
2506 .pcs = sdm845_qhp_pcie_pcs_tbl,
2527 .tx = sm8250_qmp_pcie_tx_tbl,
2531 .pcs = sm8250_qmp_pcie_pcs_tbl,
2541 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
2564 .tx = sm8250_qmp_pcie_tx_tbl,
2568 .pcs = sm8250_qmp_pcie_pcs_tbl,
2574 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
2578 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
2601 .tx = msm8998_pcie_tx_tbl,
2605 .pcs = msm8998_pcie_pcs_tbl,
2628 .tx = sc8180x_qmp_pcie_tx_tbl,
2632 .pcs = sc8180x_qmp_pcie_pcs_tbl,
2655 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
2659 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
2688 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2692 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2721 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2725 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2757 .tx = sdx55_qmp_pcie_tx_tbl,
2761 .pcs = sdx55_qmp_pcie_pcs_tbl,
2799 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
2803 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2834 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
2838 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2847 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2869 .tx = sdx65_qmp_pcie_tx_tbl,
2873 .pcs = sdx65_qmp_pcie_pcs_tbl,
2896 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
2900 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2931 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
2935 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
2973 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
2977 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3000 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
3004 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3029 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3033 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3063 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3067 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
3102 if (!(t->lane_mask & lane_mask)) in qmp_pcie_configure_lane()
3105 writel(t->val, base + t->offset); in qmp_pcie_configure_lane()
3118 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
3119 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_init_port_b()
3122 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
3123 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
3124 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
3125 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
3127 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_port_b()
3128 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_port_b()
3130 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_port_b()
3131 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_port_b()
3136 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
3137 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
3138 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers() local
3139 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
3140 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
3141 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
3142 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers() local
3143 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
3144 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
3149 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_registers()
3151 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_registers()
3152 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_registers()
3154 if (cfg->lanes >= 2) { in qmp_pcie_init_registers()
3155 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_registers()
3156 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_registers()
3159 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_registers()
3160 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_registers()
3162 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
3163 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); in qmp_pcie_init_registers()
3167 qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_registers()
3173 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
3176 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3178 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
3182 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3184 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
3188 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
3190 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
3196 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3198 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
3202 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
3209 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3211 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3219 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
3221 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
3223 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
3225 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
3233 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
3235 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on() local
3240 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_on()
3241 cfg->pwrdn_ctrl); in qmp_pcie_power_on()
3243 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
3244 mode_tbls = cfg->tbls_rc; in qmp_pcie_power_on()
3246 mode_tbls = cfg->tbls_ep; in qmp_pcie_power_on()
3248 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
3251 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3255 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
3257 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
3262 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
3264 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
3265 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_pcie_power_on()
3267 if (!cfg->skip_start_delay) in qmp_pcie_power_on()
3270 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
3271 mask = cfg->phy_status; in qmp_pcie_power_on()
3275 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
3282 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3290 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
3292 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
3295 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
3297 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
3298 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
3302 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
3303 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
3341 qmp->mode = submode; in qmp_pcie_set_mode()
3344 dev_err(&phy->dev, "Unsupported submode %d\n", submode); in qmp_pcie_set_mode()
3345 return -EINVAL; in qmp_pcie_set_mode()
3360 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
3361 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
3362 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
3365 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
3366 if (!qmp->vregs) in qmp_pcie_vreg_init()
3367 return -ENOMEM; in qmp_pcie_vreg_init()
3370 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
3372 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
3377 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
3378 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
3382 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
3383 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
3384 if (!qmp->resets) in qmp_pcie_reset_init()
3385 return -ENOMEM; in qmp_pcie_reset_init()
3387 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
3388 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
3390 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
3394 if (cfg->has_nocsr_reset) { in qmp_pcie_reset_init()
3395 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
3396 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
3397 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
3398 "failed to get no-csr reset\n"); in qmp_pcie_reset_init()
3406 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
3410 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
3411 if (!qmp->clks) in qmp_pcie_clk_init()
3412 return -ENOMEM; in qmp_pcie_clk_init()
3415 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
3417 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
3435 * +---------------+
3436 * | PHY block |<<---------------------------------------+
3438 * | +-------+ | +-----+ |
3439 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3440 * clk | +-------+ | +-----+
3441 * +---------------+
3445 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
3449 ret = of_property_read_string(np, "clock-output-names", &init.name); in phy_pipe_clk_register()
3451 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
3458 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
3461 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
3462 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
3464 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
3466 fixed->hw.init = &init; in phy_pipe_clk_register()
3468 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
3472 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); in phy_pipe_clk_register()
3480 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in phy_pipe_clk_register()
3485 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
3486 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
3487 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
3490 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
3491 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
3492 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
3496 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_parse_dt_legacy()
3497 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_parse_dt_legacy()
3498 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_parse_dt_legacy()
3500 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
3501 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
3502 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
3504 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
3505 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
3507 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
3508 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
3509 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
3511 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
3512 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
3513 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
3515 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt_legacy()
3516 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
3517 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
3518 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
3520 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
3521 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
3522 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
3524 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
3526 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
3529 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
3530 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
3531 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
3533 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
3534 if (cfg->tbls.pcs_misc || in qmp_pcie_parse_dt_legacy()
3535 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || in qmp_pcie_parse_dt_legacy()
3536 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
3537 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
3547 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
3548 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
3549 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
3560 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
3561 "qcom,4ln-config-sel", in qmp_pcie_get_4ln_config()
3565 if (ret == -ENOENT) in qmp_pcie_get_4ln_config()
3568 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
3574 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
3578 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
3580 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
3587 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
3588 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
3589 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_parse_dt()
3590 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
3595 return -EINVAL; in qmp_pcie_parse_dt()
3605 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
3606 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
3607 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
3608 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
3609 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
3611 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt()
3612 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
3613 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
3616 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
3617 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
3618 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
3619 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
3622 if (cfg->tbls.ln_shrd) in qmp_pcie_parse_dt()
3623 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
3625 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
3626 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
3627 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
3629 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
3633 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
3642 struct device *dev = &pdev->dev; in qmp_pcie_probe()
3650 return -ENOMEM; in qmp_pcie_probe()
3652 qmp->dev = dev; in qmp_pcie_probe()
3654 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
3655 if (!qmp->cfg) in qmp_pcie_probe()
3656 return -EINVAL; in qmp_pcie_probe()
3658 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
3659 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
3674 np = of_get_next_available_child(dev->of_node, NULL); in qmp_pcie_probe()
3678 np = of_node_get(dev->of_node); in qmp_pcie_probe()
3688 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
3690 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
3691 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
3692 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
3697 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
3712 .compatible = "qcom,ipq6018-qmp-pcie-phy",
3715 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
3718 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3721 .compatible = "qcom,msm8998-qmp-pcie-phy",
3724 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
3727 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
3730 .compatible = "qcom,sc8180x-qmp-pcie-phy",
3733 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
3736 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
3739 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
3742 .compatible = "qcom,sdm845-qhp-pcie-phy",
3745 .compatible = "qcom,sdm845-qmp-pcie-phy",
3748 .compatible = "qcom,sdx55-qmp-pcie-phy",
3751 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
3754 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
3757 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
3760 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3763 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
3766 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3769 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3772 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3775 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3778 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3781 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3784 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3794 .name = "qcom-qmp-pcie-phy",