88 	void __iomem *tx0;  member
266 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
267 	writel(swing, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
268 	writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
473 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
475 	writel(0x00, edp->tx0 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
493 	writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
494 	writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
495 	writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
496 	writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
497 	writel(0x04, edp->tx0 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
523 	writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
524 	writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
525 	writel(0x00, edp->tx0 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
529 	writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
531 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
532 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
536 	writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
538 	writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
561 	writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
562 	writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
789 	edp->tx0 = devm_platform_ioremap_resource(pdev, 1);  in qcom_edp_phy_probe()
790 	if (IS_ERR(edp->tx0))  in qcom_edp_phy_probe()
791 		return PTR_ERR(edp->tx0);  in qcom_edp_phy_probe()