Lines Matching +full:sc7280 +full:- +full:dp
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
74 /* DP PHY swing and pre_emphasis tables */
176 const struct qcom_edp_cfg *cfg = edp->cfg; in qcom_edp_phy_init()
180 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
184 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_init()
190 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
193 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_phy_init()
195 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
201 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
203 if (cfg && cfg->is_dp) in qcom_edp_phy_init()
208 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
210 writel(0x00, edp->edp + DP_PHY_AUX_CFG0); in qcom_edp_phy_init()
211 writel(0x13, edp->edp + DP_PHY_AUX_CFG1); in qcom_edp_phy_init()
212 writel(0x24, edp->edp + DP_PHY_AUX_CFG2); in qcom_edp_phy_init()
213 writel(0x00, edp->edp + DP_PHY_AUX_CFG3); in qcom_edp_phy_init()
214 writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); in qcom_edp_phy_init()
215 writel(0x26, edp->edp + DP_PHY_AUX_CFG5); in qcom_edp_phy_init()
216 writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); in qcom_edp_phy_init()
217 writel(0x03, edp->edp + DP_PHY_AUX_CFG7); in qcom_edp_phy_init()
218 writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); in qcom_edp_phy_init()
219 writel(0x03, edp->edp + DP_PHY_AUX_CFG9); in qcom_edp_phy_init()
223 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK); in qcom_edp_phy_init()
230 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
237 const struct qcom_edp_cfg *cfg = edp->cfg; in qcom_edp_set_voltages()
248 for (i = 0; i < dp_opts->lanes; i++) { in qcom_edp_set_voltages()
249 v_level = max(v_level, dp_opts->voltage[i]); in qcom_edp_set_voltages()
250 p_level = max(p_level, dp_opts->pre[i]); in qcom_edp_set_voltages()
253 if (dp_opts->link_rate <= 2700) { in qcom_edp_set_voltages()
254 swing = (*cfg->swing_hbr_rbr)[v_level][p_level]; in qcom_edp_set_voltages()
255 emph = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; in qcom_edp_set_voltages()
257 swing = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; in qcom_edp_set_voltages()
258 emph = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; in qcom_edp_set_voltages()
262 return -EINVAL; in qcom_edp_set_voltages()
264 ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; in qcom_edp_set_voltages()
266 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
267 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
268 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
270 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
271 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
272 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
279 const struct phy_configure_opts_dp *dp_opts = &opts->dp; in qcom_edp_phy_configure()
283 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_edp_phy_configure()
285 if (dp_opts->set_voltages) in qcom_edp_phy_configure()
293 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_configure_ssc()
297 switch (dp_opts->link_rate) { in qcom_edp_configure_ssc()
312 return -EINVAL; in qcom_edp_configure_ssc()
315 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); in qcom_edp_configure_ssc()
316 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); in qcom_edp_configure_ssc()
317 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); in qcom_edp_configure_ssc()
318 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); in qcom_edp_configure_ssc()
319 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_configure_ssc()
320 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_configure_ssc()
327 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_configure_pll()
335 switch (dp_opts->link_rate) { in qcom_edp_configure_pll()
374 return -EINVAL; in qcom_edp_configure_pll()
377 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); in qcom_edp_configure_pll()
378 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); in qcom_edp_configure_pll()
379 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); in qcom_edp_configure_pll()
380 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); in qcom_edp_configure_pll()
381 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); in qcom_edp_configure_pll()
382 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); in qcom_edp_configure_pll()
383 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); in qcom_edp_configure_pll()
384 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); in qcom_edp_configure_pll()
385 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); in qcom_edp_configure_pll()
386 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); in qcom_edp_configure_pll()
387 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); in qcom_edp_configure_pll()
388 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); in qcom_edp_configure_pll()
389 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); in qcom_edp_configure_pll()
390 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); in qcom_edp_configure_pll()
391 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); in qcom_edp_configure_pll()
392 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); in qcom_edp_configure_pll()
393 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); in qcom_edp_configure_pll()
394 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_configure_pll()
395 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_configure_pll()
396 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); in qcom_edp_configure_pll()
397 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); in qcom_edp_configure_pll()
398 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); in qcom_edp_configure_pll()
400 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); in qcom_edp_configure_pll()
401 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); in qcom_edp_configure_pll()
402 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); in qcom_edp_configure_pll()
403 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_configure_pll()
404 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); in qcom_edp_configure_pll()
405 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); in qcom_edp_configure_pll()
406 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); in qcom_edp_configure_pll()
413 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_set_vco_div()
416 switch (dp_opts->link_rate) { in qcom_edp_set_vco_div()
439 return -EINVAL; in qcom_edp_set_vco_div()
442 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); in qcom_edp_set_vco_div()
450 const struct qcom_edp_cfg *cfg = edp->cfg; in qcom_edp_phy_power_on()
462 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on()
463 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on()
465 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, in qcom_edp_phy_power_on()
471 ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; in qcom_edp_phy_power_on()
473 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
474 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
475 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
476 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
478 if (edp->dp_opts.ssc) { in qcom_edp_phy_power_on()
489 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); in qcom_edp_phy_power_on()
490 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); in qcom_edp_phy_power_on()
492 /* TX-0 register configuration */ in qcom_edp_phy_power_on()
493 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
494 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
495 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
496 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
497 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
499 /* TX-1 register configuration */ in qcom_edp_phy_power_on()
500 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
501 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
502 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
503 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
504 writel(0x04, edp->tx1 + TXn_TX_BAND); in qcom_edp_phy_power_on()
510 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
511 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
512 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
513 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
515 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_edp_phy_power_on()
517 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, in qcom_edp_phy_power_on()
522 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
523 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
524 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
525 writel(0x00, edp->tx0 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
526 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
527 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
528 writel(0x00, edp->tx1 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
529 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
530 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
531 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
532 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
533 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
534 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
536 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
537 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
538 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
539 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
541 if (edp->dp_opts.lanes == 1) { in qcom_edp_phy_power_on()
547 } else if (edp->dp_opts.lanes == 2) { in qcom_edp_phy_power_on()
561 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
562 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
563 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
564 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
565 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
567 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
570 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
572 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, in qcom_edp_phy_power_on()
577 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); in qcom_edp_phy_power_on()
578 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); in qcom_edp_phy_power_on()
587 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_off()
596 clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_exit()
597 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_exit()
614 * +------------------------------+
617 * | +-------------------+ |
619 * | +---------+---------+ |
621 * | +----------+-----------+ |
623 * | +----------+-----------+ |
624 * +------------------------------+
626 * +---------<---------v------------>----------+
628 * +--------v----------------+ |
631 * +--------+----------------+ |
640 * +--------<------------+-----------------+---<---+
642 * +----v---------+ +--------v-----+ +--------v------+
647 * +-------+------+ +-----+--------+ +--------+------+
649 * v---->----------v-------------<------v
651 * +----------+-----------------+
653 * +---------+------------------+
663 switch (req->rate) { in qcom_edp_dp_pixel_clk_determine_rate()
670 return -EINVAL; in qcom_edp_dp_pixel_clk_determine_rate()
678 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_pixel_clk_recalc_rate()
680 switch (dp_opts->link_rate) { in qcom_edp_dp_pixel_clk_recalc_rate()
702 switch (req->rate) { in qcom_edp_dp_link_clk_determine_rate()
710 return -EINVAL; in qcom_edp_dp_link_clk_determine_rate()
718 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_link_clk_recalc_rate()
720 switch (dp_opts->link_rate) { in qcom_edp_dp_link_clk_recalc_rate()
725 return dp_opts->link_rate * 100000; in qcom_edp_dp_link_clk_recalc_rate()
744 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); in qcom_edp_clks_register()
746 return -ENOMEM; in qcom_edp_clks_register()
747 data->num = 2; in qcom_edp_clks_register()
749 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
752 edp->dp_link_hw.init = &init; in qcom_edp_clks_register()
753 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); in qcom_edp_clks_register()
757 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
760 edp->dp_pixel_hw.init = &init; in qcom_edp_clks_register()
761 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); in qcom_edp_clks_register()
765 data->hws[0] = &edp->dp_link_hw; in qcom_edp_clks_register()
766 data->hws[1] = &edp->dp_pixel_hw; in qcom_edp_clks_register()
768 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); in qcom_edp_clks_register()
774 struct device *dev = &pdev->dev; in qcom_edp_phy_probe()
780 return -ENOMEM; in qcom_edp_phy_probe()
782 edp->dev = dev; in qcom_edp_phy_probe()
783 edp->cfg = of_device_get_match_data(&pdev->dev); in qcom_edp_phy_probe()
785 edp->edp = devm_platform_ioremap_resource(pdev, 0); in qcom_edp_phy_probe()
786 if (IS_ERR(edp->edp)) in qcom_edp_phy_probe()
787 return PTR_ERR(edp->edp); in qcom_edp_phy_probe()
789 edp->tx0 = devm_platform_ioremap_resource(pdev, 1); in qcom_edp_phy_probe()
790 if (IS_ERR(edp->tx0)) in qcom_edp_phy_probe()
791 return PTR_ERR(edp->tx0); in qcom_edp_phy_probe()
793 edp->tx1 = devm_platform_ioremap_resource(pdev, 2); in qcom_edp_phy_probe()
794 if (IS_ERR(edp->tx1)) in qcom_edp_phy_probe()
795 return PTR_ERR(edp->tx1); in qcom_edp_phy_probe()
797 edp->pll = devm_platform_ioremap_resource(pdev, 3); in qcom_edp_phy_probe()
798 if (IS_ERR(edp->pll)) in qcom_edp_phy_probe()
799 return PTR_ERR(edp->pll); in qcom_edp_phy_probe()
801 edp->clks[0].id = "aux"; in qcom_edp_phy_probe()
802 edp->clks[1].id = "cfg_ahb"; in qcom_edp_phy_probe()
803 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_probe()
807 edp->supplies[0].supply = "vdda-phy"; in qcom_edp_phy_probe()
808 edp->supplies[1].supply = "vdda-pll"; in qcom_edp_phy_probe()
809 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_probe()
813 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ in qcom_edp_phy_probe()
815 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); in qcom_edp_phy_probe()
819 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ in qcom_edp_phy_probe()
821 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); in qcom_edp_phy_probe()
825 ret = qcom_edp_clks_register(edp, pdev->dev.of_node); in qcom_edp_phy_probe()
829 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops); in qcom_edp_phy_probe()
830 if (IS_ERR(edp->phy)) { in qcom_edp_phy_probe()
832 return PTR_ERR(edp->phy); in qcom_edp_phy_probe()
835 phy_set_drvdata(edp->phy, edp); in qcom_edp_phy_probe()
842 { .compatible = "qcom,sc7280-edp-phy" },
843 { .compatible = "qcom,sc8180x-edp-phy" },
844 { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_phy_cfg },
845 { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg },
853 .name = "qcom-edp-phy",