Lines Matching refs:sdx5_rmw
1172 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1), in sparx5_sd25g28_apply_params()
1177 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), in sparx5_sd25g28_apply_params()
1182 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET in sparx5_sd25g28_apply_params()
1190 sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET in sparx5_sd25g28_apply_params()
1196 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), in sparx5_sd25g28_apply_params()
1201 sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET in sparx5_sd25g28_apply_params()
1207 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), in sparx5_sd25g28_apply_params()
1212 sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET in sparx5_sd25g28_apply_params()
1218 sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET in sparx5_sd25g28_apply_params()
1224 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), in sparx5_sd25g28_apply_params()
1229 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1), in sparx5_sd25g28_apply_params()
1234 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), in sparx5_sd25g28_apply_params()
1239 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1), in sparx5_sd25g28_apply_params()
1244 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1249 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1), in sparx5_sd25g28_apply_params()
1254 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), in sparx5_sd25g28_apply_params()
1259 sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET in sparx5_sd25g28_apply_params()
1268 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | in sparx5_sd25g28_apply_params()
1276 sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET in sparx5_sd25g28_apply_params()
1282 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), in sparx5_sd25g28_apply_params()
1287 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), in sparx5_sd25g28_apply_params()
1292 sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET in sparx5_sd25g28_apply_params()
1298 sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET in sparx5_sd25g28_apply_params()
1304 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET in sparx5_sd25g28_apply_params()
1310 sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET in sparx5_sd25g28_apply_params()
1316 sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET in sparx5_sd25g28_apply_params()
1322 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd25g28_apply_params()
1327 sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET in sparx5_sd25g28_apply_params()
1333 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1338 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), in sparx5_sd25g28_apply_params()
1343 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), in sparx5_sd25g28_apply_params()
1348 sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET in sparx5_sd25g28_apply_params()
1354 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), in sparx5_sd25g28_apply_params()
1359 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), in sparx5_sd25g28_apply_params()
1364 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd25g28_apply_params()
1371 sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET in sparx5_sd25g28_apply_params()
1377 sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET in sparx5_sd25g28_apply_params()
1383 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), in sparx5_sd25g28_apply_params()
1388 sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET in sparx5_sd25g28_apply_params()
1394 sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET in sparx5_sd25g28_apply_params()
1400 sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET in sparx5_sd25g28_apply_params()
1406 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), in sparx5_sd25g28_apply_params()
1411 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), in sparx5_sd25g28_apply_params()
1416 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), in sparx5_sd25g28_apply_params()
1421 sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET in sparx5_sd25g28_apply_params()
1427 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), in sparx5_sd25g28_apply_params()
1432 sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET in sparx5_sd25g28_apply_params()
1438 sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET in sparx5_sd25g28_apply_params()
1444 sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET in sparx5_sd25g28_apply_params()
1450 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | in sparx5_sd25g28_apply_params()
1457 sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET in sparx5_sd25g28_apply_params()
1463 sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET in sparx5_sd25g28_apply_params()
1469 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET in sparx5_sd25g28_apply_params()
1477 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET in sparx5_sd25g28_apply_params()
1483 sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET in sparx5_sd25g28_apply_params()
1489 sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET in sparx5_sd25g28_apply_params()
1495 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1500 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET in sparx5_sd25g28_apply_params()
1506 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), in sparx5_sd25g28_apply_params()
1511 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | in sparx5_sd25g28_apply_params()
1518 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | in sparx5_sd25g28_apply_params()
1525 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), in sparx5_sd25g28_apply_params()
1530 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd25g28_apply_params()
1535 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), in sparx5_sd25g28_apply_params()
1540 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1), in sparx5_sd25g28_apply_params()
1545 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd25g28_apply_params()
1550 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1557 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1), in sparx5_sd25g28_apply_params()
1564 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), in sparx5_sd25g28_apply_params()
1584 sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), in sparx5_sd25g28_apply_params()
1589 sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1594 sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1599 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), in sparx5_sd25g28_apply_params()
1604 sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET in sparx5_sd25g28_apply_params()
1610 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), in sparx5_sd25g28_apply_params()
1615 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), in sparx5_sd25g28_apply_params()
1663 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1), in sparx5_sd10g28_apply_params()
1706 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | in sparx5_sd10g28_apply_params()
2033 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd10g28_apply_params()
2043 sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1), in sparx5_sd10g28_apply_params()
2048 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2053 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2058 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2072 sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2077 sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2190 sdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq), in sparx5_serdes_clock_config()