948 	sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),  in sparx5_cmu_apply_cfg()
953 	sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),  in sparx5_cmu_apply_cfg()
958 	sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),  in sparx5_cmu_apply_cfg()
963 	sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |  in sparx5_cmu_apply_cfg()
976 	sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),  in sparx5_cmu_apply_cfg()
981 	sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),  in sparx5_cmu_apply_cfg()
986 	sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),  in sparx5_cmu_apply_cfg()
991 	sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),  in sparx5_cmu_apply_cfg()
996 	sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),  in sparx5_cmu_apply_cfg()
1001 	sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),  in sparx5_cmu_apply_cfg()
1006 	sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),  in sparx5_cmu_apply_cfg()
1011 	sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),  in sparx5_cmu_apply_cfg()
1016 	sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),  in sparx5_cmu_apply_cfg()
1023 	sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),  in sparx5_cmu_apply_cfg()
1028 	sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),  in sparx5_cmu_apply_cfg()
1042 	sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),  in sparx5_cmu_apply_cfg()
1108 		sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),  in sparx5_serdes_cmu_power_off()
1112 		sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0),  in sparx5_serdes_cmu_power_off()
1116 		sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0),  in sparx5_serdes_cmu_power_off()
1120 		sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1),  in sparx5_serdes_cmu_power_off()
1124 		sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0),  in sparx5_serdes_cmu_power_off()
1128 		sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1),  in sparx5_serdes_cmu_power_off()
1132 		sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) |  in sparx5_serdes_cmu_power_off()
1140 		sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1),  in sparx5_serdes_cmu_power_off()
1668 	sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) |  in sparx5_sd10g28_apply_params()
1681 	sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) |  in sparx5_sd10g28_apply_params()
1692 	sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1),  in sparx5_sd10g28_apply_params()
1697 	sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) |  in sparx5_sd10g28_apply_params()
1713 	sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET  in sparx5_sd10g28_apply_params()
1719 	sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET  in sparx5_sd10g28_apply_params()
1725 	sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET  in sparx5_sd10g28_apply_params()
1734 	sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET  in sparx5_sd10g28_apply_params()
1740 	sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET  in sparx5_sd10g28_apply_params()
1746 	sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET  in sparx5_sd10g28_apply_params()
1752 	sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET  in sparx5_sd10g28_apply_params()
1758 	sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),  in sparx5_sd10g28_apply_params()
1763 	sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET  in sparx5_sd10g28_apply_params()
1774 	sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET  in sparx5_sd10g28_apply_params()
1780 	sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET  in sparx5_sd10g28_apply_params()
1786 	sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |  in sparx5_sd10g28_apply_params()
1798 	sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),  in sparx5_sd10g28_apply_params()
1803 	sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET  in sparx5_sd10g28_apply_params()
1809 	sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET  in sparx5_sd10g28_apply_params()
1815 	sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET  in sparx5_sd10g28_apply_params()
1821 	sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET  in sparx5_sd10g28_apply_params()
1827 	sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),  in sparx5_sd10g28_apply_params()
1832 	sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET  in sparx5_sd10g28_apply_params()
1841 	sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET  in sparx5_sd10g28_apply_params()
1847 	sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET  in sparx5_sd10g28_apply_params()
1853 	sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET  in sparx5_sd10g28_apply_params()
1862 	sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET  in sparx5_sd10g28_apply_params()
1868 	sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET  in sparx5_sd10g28_apply_params()
1874 	sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET  in sparx5_sd10g28_apply_params()
1880 	sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET  in sparx5_sd10g28_apply_params()
1886 	sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET  in sparx5_sd10g28_apply_params()
1892 	sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET  in sparx5_sd10g28_apply_params()
1898 	sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET  in sparx5_sd10g28_apply_params()
1904 	sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET  in sparx5_sd10g28_apply_params()
1910 	sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET  in sparx5_sd10g28_apply_params()
1916 	sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET  in sparx5_sd10g28_apply_params()
1922 	sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET  in sparx5_sd10g28_apply_params()
1928 	sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET  in sparx5_sd10g28_apply_params()
1934 	sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),  in sparx5_sd10g28_apply_params()
1939 	sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET  in sparx5_sd10g28_apply_params()
1945 	sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET  in sparx5_sd10g28_apply_params()
1951 	sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET  in sparx5_sd10g28_apply_params()
1957 	sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET  in sparx5_sd10g28_apply_params()
1963 	sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET  in sparx5_sd10g28_apply_params()
1969 	sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET  in sparx5_sd10g28_apply_params()
1975 	sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET  in sparx5_sd10g28_apply_params()
1981 	sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET  in sparx5_sd10g28_apply_params()
1987 	sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET  in sparx5_sd10g28_apply_params()
1996 	sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET  in sparx5_sd10g28_apply_params()
2002 	sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET  in sparx5_sd10g28_apply_params()
2008 	sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET  in sparx5_sd10g28_apply_params()
2017 	sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET  in sparx5_sd10g28_apply_params()
2026 	sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |  in sparx5_sd10g28_apply_params()
2038 	sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),  in sparx5_sd10g28_apply_params()
2147 		sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),  in sparx5_serdes_power_save()
2152 		sdx5_inst_rmw(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),  in sparx5_serdes_power_save()
2156 		sdx5_inst_rmw(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(pwdn),  in sparx5_serdes_power_save()
2165 		sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),  in sparx5_serdes_power_save()
2170 		sdx5_inst_rmw(SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),  in sparx5_serdes_power_save()
2174 		sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(pwdn),  in sparx5_serdes_power_save()