Lines Matching refs:DSI_SW_CTL_EN
40 #define DSI_SW_CTL_EN BIT(0) macro
143 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
144 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
145 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
146 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
147 mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
163 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
164 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
165 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
166 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
167 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()