33 #define HDMI_CON6	0x18  macro
56 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_pll_prepare()
57 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_prepare()
60 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_pll_prepare()
84 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_pll_unprepare()
87 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_unprepare()
88 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_pll_unprepare()
113 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);  in mtk_hdmi_pll_set_rate()
114 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_set_rate()
116 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);  in mtk_hdmi_pll_set_rate()
117 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);  in mtk_hdmi_pll_set_rate()
119 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);  in mtk_hdmi_pll_set_rate()
120 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);  in mtk_hdmi_pll_set_rate()
122 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);  in mtk_hdmi_pll_set_rate()
123 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);  in mtk_hdmi_pll_set_rate()
124 	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);  in mtk_hdmi_pll_set_rate()
142 	tmp = readl(hdmi_phy->regs + HDMI_CON6);  in mtk_hdmi_pll_recalc_rate()
182 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_phy_enable_tmds()
183 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_phy_enable_tmds()
186 	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_phy_enable_tmds()
208 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_phy_disable_tmds()
211 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_phy_disable_tmds()
212 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_phy_disable_tmds()