10 #define HDMI_CON0	0x00  macro
62 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_pll_prepare()
65 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_pll_prepare()
66 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_pll_prepare()
67 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_pll_prepare()
77 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_pll_unprepare()
78 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_pll_unprepare()
79 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_pll_unprepare()
82 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_pll_unprepare()
128 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);  in mtk_hdmi_pll_set_rate()
131 	mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);  in mtk_hdmi_pll_set_rate()
188 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_phy_enable_tmds()
191 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_phy_enable_tmds()
192 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_phy_enable_tmds()
193 	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_phy_enable_tmds()
201 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_phy_disable_tmds()
202 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_phy_disable_tmds()
203 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_phy_disable_tmds()
206 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_phy_disable_tmds()