Lines Matching refs:PHY_R4
41 #define PHY_R4 0x10 macro
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
90 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
112 regmap_write(priv->regmap, PHY_R4, 0); in phy_g12a_usb3_pcie_cr_bus_read()
113 regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ); in phy_g12a_usb3_pcie_cr_bus_read()
123 regmap_write(priv->regmap, PHY_R4, 0); in phy_g12a_usb3_pcie_cr_bus_read()
147 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_write()
148 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_write()
150 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA); in phy_g12a_usb3_pcie_cr_bus_write()
158 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_write()
166 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_write()
168 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE); in phy_g12a_usb3_pcie_cr_bus_write()
176 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_write()