Lines Matching refs:HISI_UC_EVENT_CTRL_REG
32 #define HISI_UC_EVENT_CTRL_REG 0x1c00 macro
179 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_config_uring_channel()
187 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_config_uring_channel()
199 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_clear_uring_channel()
206 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_clear_uring_channel()
248 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_start_counters()
250 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_start_counters()
257 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_stop_counters()
259 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_stop_counters()
268 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_enable_counter()
270 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_enable_counter()
279 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_disable_counter()
281 writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_disable_counter()
294 val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); in hisi_uc_pmu_get_glb_en_state()