133 	freeze_for_enable = FIELD_GET(CXL_PMU_CAP_WRITEABLE_WHEN_FROZEN, val) &&  in cxl_pmu_parse_caps()
134 		FIELD_GET(CXL_PMU_CAP_FREEZE, val);  in cxl_pmu_parse_caps()
140 	info->num_counters = FIELD_GET(CXL_PMU_CAP_NUM_COUNTERS_MSK, val) + 1;  in cxl_pmu_parse_caps()
141 	info->counter_width = FIELD_GET(CXL_PMU_CAP_COUNTER_WIDTH_MSK, val);  in cxl_pmu_parse_caps()
142 	info->num_event_capabilities = FIELD_GET(CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;  in cxl_pmu_parse_caps()
144 	info->filter_hdm = FIELD_GET(CXL_PMU_CAP_FILTERS_SUP_MSK, val) & CXL_PMU_FILTER_HDM;  in cxl_pmu_parse_caps()
145 	if (FIELD_GET(CXL_PMU_CAP_INT, val))  in cxl_pmu_parse_caps()
146 		info->irq = FIELD_GET(CXL_PMU_CAP_MSI_N_MSK, val);  in cxl_pmu_parse_caps()
158 		if (FIELD_GET(CXL_PMU_COUNTER_CFG_TYPE_MSK, val) ==  in cxl_pmu_parse_caps()
163 		if (FIELD_GET(CXL_PMU_COUNTER_CFG_TYPE_MSK, val) !=  in cxl_pmu_parse_caps()
168 		group_idx = FIELD_GET(CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);  in cxl_pmu_parse_caps()
169 		events_msk = FIELD_GET(CXL_PMU_COUNTER_CFG_EVENTS_MSK, val);  in cxl_pmu_parse_caps()
175 		pmu_ev->vid = FIELD_GET(CXL_PMU_EVENT_CAP_VENDOR_ID_MSK, eval);  in cxl_pmu_parse_caps()
176 		pmu_ev->gid = FIELD_GET(CXL_PMU_EVENT_CAP_GROUP_ID_MSK, eval);  in cxl_pmu_parse_caps()
200 			pmu_ev->vid = FIELD_GET(CXL_PMU_EVENT_CAP_VENDOR_ID_MSK, eval);  in cxl_pmu_parse_caps()
201 			pmu_ev->gid = FIELD_GET(CXL_PMU_EVENT_CAP_GROUP_ID_MSK, eval);  in cxl_pmu_parse_caps()
202 			pmu_ev->msk = FIELD_GET(CXL_PMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);  in cxl_pmu_parse_caps()
288 	return FIELD_GET(CXL_PMU_ATTR_CONFIG_MASK_MSK, event->attr.config);  in cxl_pmu_config_get_mask()
293 	return FIELD_GET(CXL_PMU_ATTR_CONFIG_GID_MSK, event->attr.config);  in cxl_pmu_config_get_gid()
298 	return FIELD_GET(CXL_PMU_ATTR_CONFIG_VID_MSK, event->attr.config);  in cxl_pmu_config_get_vid()
303 	return FIELD_GET(CXL_PMU_ATTR_CONFIG1_THRESHOLD_MSK, event->attr.config1);  in cxl_pmu_config1_get_threshold()
308 	return FIELD_GET(CXL_PMU_ATTR_CONFIG1_INVERT_MSK, event->attr.config1);  in cxl_pmu_config1_get_invert()
313 	return FIELD_GET(CXL_PMU_ATTR_CONFIG1_EDGE_MSK, event->attr.config1);  in cxl_pmu_config1_get_edge()
325 	return FIELD_GET(CXL_PMU_ATTR_CONFIG1_FILTER_EN_MSK, event->attr.config1);  in cxl_pmu_config1_hdm_filter_en()
330 	return FIELD_GET(CXL_PMU_ATTR_CONFIG2_HDM_MSK, event->attr.config2);  in cxl_pmu_config2_get_hdm_decoder()
480 	int vid = FIELD_GET(CXL_PMU_ATTR_CONFIG_VID_MSK, pmu_attr->id);  in cxl_pmu_event_is_visible()
481 	int gid = FIELD_GET(CXL_PMU_ATTR_CONFIG_GID_MSK, pmu_attr->id);  in cxl_pmu_event_is_visible()
482 	int msk = FIELD_GET(CXL_PMU_ATTR_CONFIG_MASK_MSK, pmu_attr->id);  in cxl_pmu_event_is_visible()