Lines Matching refs:dev
79 bool pcie_failed_link_retrain(struct pci_dev *dev) in pcie_failed_link_retrain() argument
87 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || in pcie_failed_link_retrain()
88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
91 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); in pcie_failed_link_retrain()
92 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); in pcie_failed_link_retrain()
95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
99 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); in pcie_failed_link_retrain()
101 if (pcie_retrain_link(dev, false)) { in pcie_failed_link_retrain()
102 pci_info(dev, "retraining failed\n"); in pcie_failed_link_retrain()
106 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); in pcie_failed_link_retrain()
111 pci_match_id(ids, dev)) { in pcie_failed_link_retrain()
114 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); in pcie_failed_link_retrain()
115 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); in pcie_failed_link_retrain()
118 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); in pcie_failed_link_retrain()
120 if (pcie_retrain_link(dev, false)) { in pcie_failed_link_retrain()
121 pci_info(dev, "retraining failed\n"); in pcie_failed_link_retrain()
129 static ktime_t fixup_debug_start(struct pci_dev *dev, in fixup_debug_start() argument
130 void (*fn)(struct pci_dev *dev)) in fixup_debug_start() argument
133 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); in fixup_debug_start()
138 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, in fixup_debug_report() argument
139 void (*fn)(struct pci_dev *dev)) in fixup_debug_report() argument
148 pci_info(dev, "%pS took %lld usecs\n", fn, duration); in fixup_debug_report()
151 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, in pci_do_fixups() argument
157 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
159 (f->vendor == dev->vendor || in pci_do_fixups()
161 (f->device == dev->device || in pci_do_fixups()
163 void (*hook)(struct pci_dev *dev); in pci_do_fixups()
169 calltime = fixup_debug_start(dev, hook); in pci_do_fixups()
170 hook(dev); in pci_do_fixups()
171 fixup_debug_report(dev, calltime, hook); in pci_do_fixups()
194 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) in pci_fixup_device() argument
245 pci_do_fixups(dev, start, end); in pci_fixup_device()
251 struct pci_dev *dev = NULL; in pci_apply_final_quirks() local
259 for_each_pci_dev(dev) { in pci_apply_final_quirks()
260 pci_fixup_device(pci_fixup_final, dev); in pci_apply_final_quirks()
267 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); in pci_apply_final_quirks()
273 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", in pci_apply_final_quirks()
296 static void quirk_mmio_always_on(struct pci_dev *dev) in quirk_mmio_always_on() argument
298 dev->mmio_always_on = 1; in quirk_mmio_always_on()
314 static void quirk_passive_release(struct pci_dev *dev) in quirk_passive_release() argument
344 static void quirk_isa_dma_hangs(struct pci_dev *dev) in quirk_isa_dma_hangs() argument
348 pci_info(dev, "Activating ISA DMA hang workarounds\n"); in quirk_isa_dma_hangs()
369 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) in quirk_tigerpoint_bm_sts() argument
374 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
379 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); in quirk_tigerpoint_bm_sts()
387 static void quirk_nopcipci(struct pci_dev *dev) in quirk_nopcipci() argument
390 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
397 static void quirk_nopciamd(struct pci_dev *dev) in quirk_nopciamd() argument
400 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
403 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
410 static void quirk_triton(struct pci_dev *dev) in quirk_triton() argument
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
432 static void quirk_vialatency(struct pci_dev *dev) in quirk_vialatency() argument
473 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
481 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
482 pci_info(dev, "Applying VIA southbridge workaround\n"); in quirk_vialatency()
495 static void quirk_viaetbf(struct pci_dev *dev) in quirk_viaetbf() argument
498 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
504 static void quirk_vsfx(struct pci_dev *dev) in quirk_vsfx() argument
507 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
518 static void quirk_alimagik(struct pci_dev *dev) in quirk_alimagik() argument
521 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
529 static void quirk_natoma(struct pci_dev *dev) in quirk_natoma() argument
532 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
547 static void quirk_citrine(struct pci_dev *dev) in quirk_citrine() argument
549 dev->cfg_size = 0xA0; in quirk_citrine()
557 static void quirk_nfp6000(struct pci_dev *dev) in quirk_nfp6000() argument
559 dev->cfg_size = 0x600; in quirk_nfp6000()
567 static void quirk_extend_bar_to_page(struct pci_dev *dev) in quirk_extend_bar_to_page() argument
572 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
578 pci_info(dev, "expanded BAR %d to page size: %pR\n", in quirk_extend_bar_to_page()
589 static void quirk_s3_64M(struct pci_dev *dev) in quirk_s3_64M() argument
591 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
602 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, in quirk_io() argument
607 struct resource *res = dev->resource + pos; in quirk_io()
609 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); in quirk_io()
614 res->name = pci_name(dev); in quirk_io()
623 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
625 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", in quirk_io()
638 static void quirk_cs5536_vsa(struct pci_dev *dev) in quirk_cs5536_vsa() argument
642 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
643 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
644 quirk_io(dev, 1, 256, name); /* GPIO */ in quirk_cs5536_vsa()
645 quirk_io(dev, 2, 64, name); /* MFGPT */ in quirk_cs5536_vsa()
646 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", in quirk_cs5536_vsa()
652 static void quirk_io_region(struct pci_dev *dev, int port, in quirk_io_region() argument
657 struct resource *res = dev->resource + nr; in quirk_io_region()
659 pci_read_config_word(dev, port, ®ion); in quirk_io_region()
665 res->name = pci_name(dev); in quirk_io_region()
671 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
673 if (!pci_claim_resource(dev, nr)) in quirk_io_region()
674 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); in quirk_io_region()
681 static void quirk_ati_exploding_mce(struct pci_dev *dev) in quirk_ati_exploding_mce() argument
683 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
753 static void quirk_ali7101_acpi(struct pci_dev *dev) in quirk_ali7101_acpi() argument
755 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
756 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
760 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int e… in piix4_io_quirk() argument
765 pci_read_config_dword(dev, port, &devres); in piix4_io_quirk()
783 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
786 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int … in piix4_mem_quirk() argument
791 pci_read_config_dword(dev, port, &devres); in piix4_mem_quirk()
809 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
818 static void quirk_piix4_acpi(struct pci_dev *dev) in quirk_piix4_acpi() argument
822 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
823 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
826 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
828 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
829 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
835 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
836 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
840 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
841 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
843 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
844 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
865 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) in quirk_ich4_lpc_acpi() argument
876 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in quirk_ich4_lpc_acpi()
878 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in quirk_ich4_lpc_acpi()
881 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); in quirk_ich4_lpc_acpi()
883 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in quirk_ich4_lpc_acpi()
897 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) in ich6_lpc_acpi_gpio() argument
901 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in ich6_lpc_acpi_gpio()
903 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in ich6_lpc_acpi_gpio()
906 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); in ich6_lpc_acpi_gpio()
908 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in ich6_lpc_acpi_gpio()
912 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, in ich6_lpc_generic_decode() argument
918 pci_read_config_dword(dev, reg, &val); in ich6_lpc_generic_decode()
941 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
944 static void quirk_ich6_lpc(struct pci_dev *dev) in quirk_ich6_lpc() argument
947 ich6_lpc_acpi_gpio(dev); in quirk_ich6_lpc()
950 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
951 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
956 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, in ich7_lpc_generic_decode() argument
962 pci_read_config_dword(dev, reg, &val); in ich7_lpc_generic_decode()
977 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); in ich7_lpc_generic_decode()
981 static void quirk_ich7_lpc(struct pci_dev *dev) in quirk_ich7_lpc() argument
984 ich6_lpc_acpi_gpio(dev); in quirk_ich7_lpc()
987 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
988 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
989 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
990 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1010 static void quirk_vt82c586_acpi(struct pci_dev *dev) in quirk_vt82c586_acpi() argument
1012 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1013 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
1024 static void quirk_vt82c686_acpi(struct pci_dev *dev) in quirk_vt82c686_acpi() argument
1026 quirk_vt82c586_acpi(dev); in quirk_vt82c686_acpi()
1028 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
1031 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
1040 static void quirk_vt8235_acpi(struct pci_dev *dev) in quirk_vt8235_acpi() argument
1042 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
1043 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
1051 static void quirk_xio2000a(struct pci_dev *dev) in quirk_xio2000a() argument
1056 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1057 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1077 static void quirk_via_ioapic(struct pci_dev *dev) in quirk_via_ioapic() argument
1086 pci_info(dev, "%s VIA external APIC routing\n", in quirk_via_ioapic()
1090 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1101 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) in quirk_via_vt8237_bypass_apic_deassert() argument
1106 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1108 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1109 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1124 static void quirk_amd_ioapic(struct pci_dev *dev) in quirk_amd_ioapic() argument
1126 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1127 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); in quirk_amd_ioapic()
1128 pci_warn(dev, " : booting with the \"noapic\" option\n"); in quirk_amd_ioapic()
1136 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) in quirk_cavium_sriov_rnm_link() argument
1139 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1140 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1149 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) in quirk_amd_8131_mmrbc() argument
1151 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1152 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1153 dev->revision); in quirk_amd_8131_mmrbc()
1154 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1182 static void quirk_via_bridge(struct pci_dev *dev) in quirk_via_bridge() argument
1185 switch (dev->device) { in quirk_via_bridge()
1192 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1193 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1230 static void quirk_via_vlink(struct pci_dev *dev) in quirk_via_vlink() argument
1238 new_irq = dev->irq; in quirk_via_vlink()
1245 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1246 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1253 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in quirk_via_vlink()
1255 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", in quirk_via_vlink()
1258 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); in quirk_via_vlink()
1268 static void quirk_vt82c598_id(struct pci_dev *dev) in quirk_vt82c598_id() argument
1270 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1271 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1281 static void quirk_cardbus_legacy(struct pci_dev *dev) in quirk_cardbus_legacy() argument
1283 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1297 static void quirk_amd_ordering(struct pci_dev *dev) in quirk_amd_ordering() argument
1300 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1303 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
1304 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1305 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1307 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1320 static void quirk_dunord(struct pci_dev *dev) in quirk_dunord() argument
1322 struct resource *r = &dev->resource[1]; in quirk_dunord()
1335 static void quirk_transparent_bridge(struct pci_dev *dev) in quirk_transparent_bridge() argument
1337 dev->transparent = 1; in quirk_transparent_bridge()
1348 static void quirk_mediagx_master(struct pci_dev *dev) in quirk_mediagx_master() argument
1352 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1355 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1357 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1462 static void quirk_eisa_bridge(struct pci_dev *dev) in quirk_eisa_bridge() argument
1464 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1495 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) in asus_hides_smbus_hostbridge() argument
1497 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1498 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1499 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1506 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1507 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1513 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1514 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1518 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1519 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1523 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1524 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1528 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1529 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1536 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1542 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1546 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1547 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1552 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1553 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1554 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1560 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1567 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1571 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1572 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1573 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1577 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1578 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1579 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1583 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1584 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1591 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1592 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1603 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1604 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1628 static void asus_hides_smbus_lpc(struct pci_dev *dev) in asus_hides_smbus_lpc() argument
1635 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1637 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1638 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1640 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1643 pci_info(dev, "Enabled i801 SMBus device\n"); in asus_hides_smbus_lpc()
1663 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_suspend() argument
1671 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1678 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume_early() argument
1692 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume() argument
1699 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); in asus_hides_smbus_lpc_ich6_resume()
1702 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6() argument
1704 asus_hides_smbus_lpc_ich6_suspend(dev); in asus_hides_smbus_lpc_ich6()
1705 asus_hides_smbus_lpc_ich6_resume_early(dev); in asus_hides_smbus_lpc_ich6()
1706 asus_hides_smbus_lpc_ich6_resume(dev); in asus_hides_smbus_lpc_ich6()
1714 static void quirk_sis_96x_smbus(struct pci_dev *dev) in quirk_sis_96x_smbus() argument
1717 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1719 pci_info(dev, "Enabling SiS 96x SMBus\n"); in quirk_sis_96x_smbus()
1720 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1742 static void quirk_sis_503(struct pci_dev *dev) in quirk_sis_503() argument
1747 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); in quirk_sis_503()
1748 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); in quirk_sis_503()
1749 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); in quirk_sis_503()
1751 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); in quirk_sis_503()
1760 dev->device = devid; in quirk_sis_503()
1761 quirk_sis_96x_smbus(dev); in quirk_sis_503()
1772 static void asus_hides_ac97_lpc(struct pci_dev *dev) in asus_hides_ac97_lpc() argument
1777 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1778 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1785 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1787 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1788 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1790 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1793 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); in asus_hides_ac97_lpc()
1879 static void quirk_jmicron_async_suspend(struct pci_dev *dev) in quirk_jmicron_async_suspend() argument
1881 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1882 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1883 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1917 static void quirk_no_msi(struct pci_dev *dev) in quirk_no_msi() argument
1919 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); in quirk_no_msi()
1920 dev->no_msi = 1; in quirk_no_msi()
1967 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1968 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1982 static void quirk_pcie_pxh(struct pci_dev *dev) in quirk_pcie_pxh() argument
1984 dev->no_msi = 1; in quirk_pcie_pxh()
1985 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); in quirk_pcie_pxh()
1997 static void quirk_intel_pcie_pm(struct pci_dev *dev) in quirk_intel_pcie_pm() argument
2000 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
2024 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) in quirk_d3hot_delay() argument
2026 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
2029 dev->d3hot_delay = delay; in quirk_d3hot_delay()
2030 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
2031 dev->d3hot_delay); in quirk_d3hot_delay()
2034 static void quirk_radeon_pm(struct pci_dev *dev) in quirk_radeon_pm() argument
2036 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
2037 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2038 quirk_d3hot_delay(dev, 20); in quirk_radeon_pm()
2047 static void quirk_nvidia_hda_pm(struct pci_dev *dev) in quirk_nvidia_hda_pm() argument
2049 quirk_d3hot_delay(dev, 20); in quirk_nvidia_hda_pm()
2064 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) in quirk_ryzen_xhci_d3hot() argument
2066 quirk_d3hot_delay(dev, 20); in quirk_ryzen_xhci_d3hot()
2102 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) in quirk_reroute_to_boot_interrupts_intel() argument
2108 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2109 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", in quirk_reroute_to_boot_interrupts_intel()
2110 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2154 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) in quirk_disable_intel_boot_interrupt() argument
2162 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2164 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, in quirk_disable_intel_boot_interrupt()
2167 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, in quirk_disable_intel_boot_interrupt()
2175 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, in quirk_disable_intel_boot_interrupt()
2178 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, in quirk_disable_intel_boot_interrupt()
2184 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_intel_boot_interrupt()
2185 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2230 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) in quirk_disable_broadcom_boot_interrupt() argument
2238 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
2239 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | in quirk_disable_broadcom_boot_interrupt()
2247 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
2249 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_broadcom_boot_interrupt()
2250 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2267 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_813x_boot_interrupt() argument
2273 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2274 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2277 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
2279 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
2281 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_813x_boot_interrupt()
2282 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2291 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_8111_boot_interrupt() argument
2298 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); in quirk_disable_amd_8111_boot_interrupt()
2300 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", in quirk_disable_amd_8111_boot_interrupt()
2301 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2304 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2305 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_8111_boot_interrupt()
2306 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2317 static void quirk_tc86c001_ide(struct pci_dev *dev) in quirk_tc86c001_ide() argument
2319 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2338 static void quirk_plx_pci9050(struct pci_dev *dev) in quirk_plx_pci9050() argument
2343 if (dev->revision >= 2) in quirk_plx_pci9050()
2346 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2347 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2348 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2349 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2370 static void quirk_netmos(struct pci_dev *dev) in quirk_netmos() argument
2372 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2373 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2385 switch (dev->device) { in quirk_netmos()
2388 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2389 dev->subsystem_device == 0x0299) in quirk_netmos()
2397 …pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_s… in quirk_netmos()
2398 dev->device, num_parallel, num_serial); in quirk_netmos()
2399 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2400 (dev->class & 0xff); in quirk_netmos()
2407 static void quirk_e100_interrupt(struct pci_dev *dev) in quirk_e100_interrupt() argument
2413 switch (dev->device) { in quirk_e100_interrupt()
2440 pci_read_config_word(dev, PCI_COMMAND, &command); in quirk_e100_interrupt()
2442 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2449 if (dev->pm_cap) { in quirk_e100_interrupt()
2450 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2456 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2458 pci_warn(dev, "Can't map e100 registers\n"); in quirk_e100_interrupt()
2464 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); in quirk_e100_interrupt()
2477 static void quirk_disable_aspm_l0s(struct pci_dev *dev) in quirk_disable_aspm_l0s() argument
2479 pci_info(dev, "Disabling L0s\n"); in quirk_disable_aspm_l0s()
2480 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); in quirk_disable_aspm_l0s()
2497 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) in quirk_disable_aspm_l0s_l1() argument
2499 pci_info(dev, "Disabling ASPM L0s/L1\n"); in quirk_disable_aspm_l0s_l1()
2500 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); in quirk_disable_aspm_l0s_l1()
2518 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) in quirk_enable_clear_retrain_link() argument
2520 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2521 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); in quirk_enable_clear_retrain_link()
2527 static void fixup_rev1_53c810(struct pci_dev *dev) in fixup_rev1_53c810() argument
2529 u32 class = dev->class; in fixup_rev1_53c810()
2538 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2539 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2540 class, dev->class); in fixup_rev1_53c810()
2545 static void quirk_p64h2_1k_io(struct pci_dev *dev) in quirk_p64h2_1k_io() argument
2549 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2552 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); in quirk_p64h2_1k_io()
2553 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2563 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) in quirk_nvidia_ck804_pcie_aer_ext_cap() argument
2567 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2569 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2570 pci_info(dev, "Linking AER extended capability\n"); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2579 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) in quirk_via_cx700_pci_parking_caching() argument
2605 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2608 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2610 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2614 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2617 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2620 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2623 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2625 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2631 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) in quirk_brcm_5719_limit_mrrs() argument
2635 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2639 int readrq = pcie_get_readrq(dev); in quirk_brcm_5719_limit_mrrs()
2641 pcie_set_readrq(dev, 2048); in quirk_brcm_5719_limit_mrrs()
2654 static void quirk_unhide_mch_dev6(struct pci_dev *dev) in quirk_unhide_mch_dev6() argument
2658 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2659 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); in quirk_unhide_mch_dev6()
2660 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2676 static void quirk_disable_all_msi(struct pci_dev *dev) in quirk_disable_all_msi() argument
2679 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); in quirk_disable_all_msi()
2692 static void quirk_disable_msi(struct pci_dev *dev) in quirk_disable_msi() argument
2694 if (dev->subordinate) { in quirk_disable_msi()
2695 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_disable_msi()
2696 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2727 static int msi_ht_cap_enabled(struct pci_dev *dev) in msi_ht_cap_enabled() argument
2731 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in msi_ht_cap_enabled()
2735 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in msi_ht_cap_enabled()
2737 pci_info(dev, "Found %s HT MSI Mapping\n", in msi_ht_cap_enabled()
2743 pos = pci_find_next_ht_capability(dev, pos, in msi_ht_cap_enabled()
2750 static void quirk_msi_ht_cap(struct pci_dev *dev) in quirk_msi_ht_cap() argument
2752 if (!msi_ht_cap_enabled(dev)) in quirk_msi_ht_cap()
2753 quirk_disable_msi(dev); in quirk_msi_ht_cap()
2762 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) in quirk_nvidia_ck804_msi_ht_cap() argument
2770 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2774 quirk_msi_ht_cap(dev); in quirk_nvidia_ck804_msi_ht_cap()
2781 static void ht_enable_msi_mapping(struct pci_dev *dev) in ht_enable_msi_mapping() argument
2785 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_enable_msi_mapping()
2789 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2791 pci_info(dev, "Enabling HT MSI Mapping\n"); in ht_enable_msi_mapping()
2793 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2796 pos = pci_find_next_ht_capability(dev, pos, in ht_enable_msi_mapping()
2811 static void nvenet_msi_disable(struct pci_dev *dev) in nvenet_msi_disable() argument
2818 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2819 dev->no_msi = 1; in nvenet_msi_disable()
2835 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) in pci_quirk_nvidia_tegra_disable_rp_msi() argument
2837 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2898 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) in nvbridge_check_legacy_irq_routing() argument
2902 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) in nvbridge_check_legacy_irq_routing()
2905 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2910 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2920 static int ht_check_msi_mapping(struct pci_dev *dev) in ht_check_msi_mapping() argument
2926 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_check_msi_mapping()
2932 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_check_msi_mapping()
2941 pos = pci_find_next_ht_capability(dev, pos, in ht_check_msi_mapping()
2950 struct pci_dev *dev; in host_bridge_with_leaf() local
2957 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2958 if (!dev) in host_bridge_with_leaf()
2962 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in host_bridge_with_leaf()
2964 pci_dev_put(dev); in host_bridge_with_leaf()
2968 if (ht_check_msi_mapping(dev)) { in host_bridge_with_leaf()
2970 pci_dev_put(dev); in host_bridge_with_leaf()
2973 pci_dev_put(dev); in host_bridge_with_leaf()
2982 static int is_end_of_ht_chain(struct pci_dev *dev) in is_end_of_ht_chain() argument
2988 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in is_end_of_ht_chain()
2993 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); in is_end_of_ht_chain()
2997 pci_read_config_word(dev, pos + ctrl_off, &ctrl); in is_end_of_ht_chain()
3006 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) in nv_ht_enable_msi_mapping() argument
3013 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
3015 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3031 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && in nv_ht_enable_msi_mapping()
3039 ht_enable_msi_mapping(dev); in nv_ht_enable_msi_mapping()
3045 static void ht_disable_msi_mapping(struct pci_dev *dev) in ht_disable_msi_mapping() argument
3049 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_disable_msi_mapping()
3053 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
3055 pci_info(dev, "Disabling HT MSI Mapping\n"); in ht_disable_msi_mapping()
3057 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
3060 pos = pci_find_next_ht_capability(dev, pos, in ht_disable_msi_mapping()
3065 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) in __nv_msi_ht_cap_quirk() argument
3075 found = ht_check_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3085 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3088 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
3098 ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3100 nv_ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3110 ht_disable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3116 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) in nv_msi_ht_cap_quirk_all() argument
3118 return __nv_msi_ht_cap_quirk(dev, 1); in nv_msi_ht_cap_quirk_all()
3123 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) in nv_msi_ht_cap_quirk_leaf() argument
3125 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
3130 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) in quirk_msi_intx_disable_bug() argument
3132 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3135 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) in quirk_msi_intx_disable_ati_bug() argument
3150 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3154 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) in quirk_msi_intx_disable_qca_bug() argument
3157 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3158 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); in quirk_msi_intx_disable_qca_bug()
3159 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3232 static void quirk_al_msi_disable(struct pci_dev *dev) in quirk_al_msi_disable() argument
3234 dev->no_msi = 1; in quirk_al_msi_disable()
3235 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3248 static void quirk_hotplug_bridge(struct pci_dev *dev) in quirk_hotplug_bridge() argument
3250 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3280 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) in ricoh_mmc_fixup_rl5c476() argument
3291 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3294 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3298 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3299 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3300 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3301 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3302 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3303 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3304 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3306 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); in ricoh_mmc_fixup_rl5c476()
3307 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_rl5c476()
3312 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) in ricoh_mmc_fixup_r5c832() argument
3322 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3336 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3337 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3338 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3339 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3340 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3341 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3342 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3343 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3345 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); in ricoh_mmc_fixup_r5c832()
3348 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3353 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3354 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3355 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3356 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3358 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); in ricoh_mmc_fixup_r5c832()
3359 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_r5c832()
3383 static void vtd_mask_spec_errors(struct pci_dev *dev) in vtd_mask_spec_errors() argument
3387 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); in vtd_mask_spec_errors()
3388 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); in vtd_mask_spec_errors()
3394 static void fixup_ti816x_class(struct pci_dev *dev) in fixup_ti816x_class() argument
3396 u32 class = dev->class; in fixup_ti816x_class()
3399 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3400 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3401 class, dev->class); in fixup_ti816x_class()
3410 static void fixup_mpss_256(struct pci_dev *dev) in fixup_mpss_256() argument
3412 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3430 static void quirk_intel_mc_errata(struct pci_dev *dev) in quirk_intel_mc_errata() argument
3444 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3446 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); in quirk_intel_mc_errata()
3455 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3457 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); in quirk_intel_mc_errata()
3496 static void quirk_intel_ntb(struct pci_dev *dev) in quirk_intel_ntb() argument
3501 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3505 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3507 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3511 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3529 static void disable_igfx_irq(struct pci_dev *dev) in disable_igfx_irq() argument
3531 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3533 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3539 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); in disable_igfx_irq()
3544 pci_iounmap(dev, regs); in disable_igfx_irq()
3558 static void quirk_remove_d3hot_delay(struct pci_dev *dev) in quirk_remove_d3hot_delay() argument
3560 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3594 static void quirk_broken_intx_masking(struct pci_dev *dev) in quirk_broken_intx_masking() argument
3596 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3723 static void quirk_no_bus_reset(struct pci_dev *dev) in quirk_no_bus_reset() argument
3725 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3732 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) in quirk_nvidia_no_bus_reset() argument
3734 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3735 quirk_no_bus_reset(dev); in quirk_nvidia_no_bus_reset()
3771 static void quirk_no_pm_reset(struct pci_dev *dev) in quirk_no_pm_reset() argument
3777 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3778 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3844 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) in quirk_apple_poweroff_thunderbolt() argument
3850 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) in quirk_apple_poweroff_thunderbolt()
3862 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3877 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); in quirk_apple_poweroff_thunderbolt()
3897 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) in reset_intel_82599_sfp_virtfn() argument
3908 pcie_flr(dev); in reset_intel_82599_sfp_virtfn()
3919 static int reset_ivb_igd(struct pci_dev *dev, bool probe) in reset_ivb_igd() argument
3928 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3952 pci_warn(dev, "timeout during reset\n"); in reset_ivb_igd()
3957 pci_iounmap(dev, mmio_base); in reset_ivb_igd()
3962 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) in reset_chelsio_generic_dev() argument
3971 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3987 pci_read_config_word(dev, PCI_COMMAND, &old_command); in reset_chelsio_generic_dev()
3988 pci_write_config_word(dev, PCI_COMMAND, in reset_chelsio_generic_dev()
3995 pci_save_state(dev); in reset_chelsio_generic_dev()
4004 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
4006 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
4011 pcie_flr(dev); in reset_chelsio_generic_dev()
4018 pci_restore_state(dev); in reset_chelsio_generic_dev()
4019 pci_write_config_word(dev, PCI_COMMAND, old_command); in reset_chelsio_generic_dev()
4040 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) in nvme_disable_and_flr() argument
4046 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
4047 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
4053 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
4057 pci_read_config_word(dev, PCI_COMMAND, &cmd); in nvme_disable_and_flr()
4058 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); in nvme_disable_and_flr()
4095 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); in nvme_disable_and_flr()
4101 pci_iounmap(dev, bar); in nvme_disable_and_flr()
4103 pcie_flr(dev); in nvme_disable_and_flr()
4115 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) in delay_250ms_after_flr() argument
4118 return pcie_reset_flr(dev, PCI_RESET_PROBE); in delay_250ms_after_flr()
4120 pcie_reset_flr(dev, PCI_RESET_DO_RESET); in delay_250ms_after_flr()
4213 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) in pci_dev_specific_reset() argument
4218 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4220 (i->device == dev->device || in pci_dev_specific_reset()
4222 return i->reset(dev, probe); in pci_dev_specific_reset()
4228 static void quirk_dma_func0_alias(struct pci_dev *dev) in quirk_dma_func0_alias() argument
4230 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4231 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4242 static void quirk_dma_func1_alias(struct pci_dev *dev) in quirk_dma_func1_alias() argument
4244 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4245 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4332 static void quirk_fixed_dma_alias(struct pci_dev *dev) in quirk_fixed_dma_alias() argument
4336 id = pci_match_id(fixed_dma_alias_tbl, dev); in quirk_fixed_dma_alias()
4338 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4456 static void quirk_relaxedordering_disable(struct pci_dev *dev) in quirk_relaxedordering_disable() argument
4458 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4459 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); in quirk_relaxedordering_disable()
4573 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4640 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_amd_sb_acs() argument
4647 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4666 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) in pci_quirk_cavium_acs_match() argument
4668 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_cavium_acs_match()
4671 switch (dev->device) { in pci_quirk_cavium_acs_match()
4685 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_cavium_acs() argument
4687 if (!pci_quirk_cavium_acs_match(dev)) in pci_quirk_cavium_acs()
4702 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_xgene_acs() argument
4718 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_zhaoxin_pcie_ports_acs() argument
4720 if (!pci_is_pcie(dev) || in pci_quirk_zhaoxin_pcie_ports_acs()
4721 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && in pci_quirk_zhaoxin_pcie_ports_acs()
4722 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) in pci_quirk_zhaoxin_pcie_ports_acs()
4729 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4774 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) in pci_quirk_intel_pch_acs_match() argument
4779 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_intel_pch_acs_match()
4783 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4789 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_intel_pch_acs() argument
4791 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_intel_pch_acs()
4794 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4811 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_qcom_rp_acs() argument
4823 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_nxp_rp_acs() argument
4829 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_al_acs() argument
4831 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_al_acs()
4892 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) in pci_quirk_intel_spt_pch_acs_match() argument
4894 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_intel_spt_pch_acs_match()
4897 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4909 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_intel_spt_pch_acs() argument
4914 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_intel_spt_pch_acs()
4917 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4922 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_intel_spt_pch_acs()
4925 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_intel_spt_pch_acs()
4930 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_mf_endpoint_acs() argument
4946 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_rciep_acs() argument
4953 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) in pci_quirk_rciep_acs()
4960 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_brcm_acs() argument
4979 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_wangxun_nic_acs() argument
4981 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
4995 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
5153 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) in pci_dev_specific_acs_enabled() argument
5165 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5167 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5169 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5197 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_lpc_acs() argument
5207 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5229 pci_info(dev, "Disabling UPDCR peer decodes\n"); in pci_quirk_enable_intel_lpc_acs()
5244 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_rp_mpc_acs() argument
5254 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); in pci_quirk_enable_intel_rp_mpc_acs()
5256 pci_info(dev, "Enabling MPC IRBNCE\n"); in pci_quirk_enable_intel_rp_mpc_acs()
5258 pci_write_config_word(dev, INTEL_MPC_REG, mpc); in pci_quirk_enable_intel_rp_mpc_acs()
5269 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) in pci_quirk_enable_intel_pch_acs() argument
5271 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_enable_intel_pch_acs()
5274 if (pci_quirk_enable_intel_lpc_acs(dev)) { in pci_quirk_enable_intel_pch_acs()
5275 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); in pci_quirk_enable_intel_pch_acs()
5279 pci_quirk_enable_intel_rp_mpc_acs(dev); in pci_quirk_enable_intel_pch_acs()
5281 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5283 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_pch_acs()
5288 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) in pci_quirk_enable_intel_spt_pch_acs() argument
5293 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_enable_intel_spt_pch_acs()
5296 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5300 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_enable_intel_spt_pch_acs()
5301 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_enable_intel_spt_pch_acs()
5308 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5311 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); in pci_quirk_enable_intel_spt_pch_acs()
5313 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_spt_pch_acs()
5318 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) in pci_quirk_disable_intel_spt_pch_acs_redir() argument
5323 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_disable_intel_spt_pch_acs_redir()
5326 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5330 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_disable_intel_spt_pch_acs_redir()
5331 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_disable_intel_spt_pch_acs_redir()
5335 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); in pci_quirk_disable_intel_spt_pch_acs_redir()
5337 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); in pci_quirk_disable_intel_spt_pch_acs_redir()
5345 int (*enable_acs)(struct pci_dev *dev);
5346 int (*disable_acs_redir)(struct pci_dev *dev);
5357 int pci_dev_specific_enable_acs(struct pci_dev *dev) in pci_dev_specific_enable_acs() argument
5364 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5366 (p->device == dev->device || in pci_dev_specific_enable_acs()
5369 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5378 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) in pci_dev_specific_disable_acs_redir() argument
5385 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5387 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5390 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5492 static void quirk_no_flr(struct pci_dev *dev) in quirk_no_flr() argument
5494 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5504 static void quirk_no_flr_snet(struct pci_dev *dev) in quirk_no_flr_snet() argument
5506 if (dev->revision == 0x1) in quirk_no_flr_snet()
5507 quirk_no_flr(dev); in quirk_no_flr_snet()
5632 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5640 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
6030 static void pci_fixup_no_d0_pme(struct pci_dev *dev) in pci_fixup_no_d0_pme() argument
6032 pci_info(dev, "PME# does not work under D0, disabling it\n"); in pci_fixup_no_d0_pme()
6033 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
6047 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) in pci_fixup_no_msi_no_pme() argument
6050 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); in pci_fixup_no_msi_no_pme()
6051 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
6053 pci_info(dev, "PME# is unreliable, disabling it\n"); in pci_fixup_no_msi_no_pme()
6054 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6127 static void rom_bar_overlap_defect(struct pci_dev *dev) in rom_bar_overlap_defect() argument
6129 pci_info(dev, "working around ROM BAR overlap defect\n"); in rom_bar_overlap_defect()
6130 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
6145 static void aspm_l1_acceptable_latency(struct pci_dev *dev) in aspm_l1_acceptable_latency() argument
6147 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
6150 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
6151 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", in aspm_l1_acceptable_latency()
6189 static void dpc_log_size(struct pci_dev *dev) in dpc_log_size() argument
6193 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); in dpc_log_size()
6197 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); in dpc_log_size()
6202 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); in dpc_log_size()
6203 dev->dpc_rp_log_size = 4; in dpc_log_size()