Lines Matching +full:realtek +full:- +full:smi
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
91 int ret = -ENOTTY; in pcie_failed_link_retrain()
94 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
103 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
170 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
171 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
172 (f->vendor == dev->vendor || in pci_do_fixups()
173 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
174 (f->device == dev->device || in pci_do_fixups()
175 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
178 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
180 hook = f->hook; in pci_do_fixups()
306 * key system devices. For devices that need to have mmio decoding always-on,
307 * we need to set the dev->mmio_always_on bit.
311 dev->mmio_always_on = 1; in quirk_mmio_always_on()
352 * contacts at VIA ask them for me please -- Alan
399 /* Chipsets where PCI->PCI transfers vanish or hang */
437 * Made according to a Windows driver-based patch by George E. Breese;
439 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
458 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
462 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
470 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
562 dev->cfg_size = 0xA0; in quirk_citrine()
572 dev->cfg_size = 0x600; in quirk_nfp6000()
585 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
587 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
588 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
589 r->start = 0; in quirk_extend_bar_to_page()
590 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
600 * If it's needed, re-allocate the region.
604 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
606 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
607 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
608 r->start = 0; in quirk_s3_64M()
609 r->end = 0x3ffffff; in quirk_s3_64M()
620 struct resource *res = dev->resource + pos; in quirk_io()
627 res->name = pci_name(dev); in quirk_io()
628 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
629 res->flags |= in quirk_io()
631 region &= ~(size - 1); in quirk_io()
635 bus_region.end = region + size - 1; in quirk_io()
636 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
648 * CS553x's ISA PCI BARs may also be read-only (ref:
649 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
670 struct resource *res = dev->resource + nr; in quirk_io_region()
673 region &= ~(size - 1); in quirk_io_region()
678 res->name = pci_name(dev); in quirk_io_region()
679 res->flags = IORESOURCE_IO; in quirk_io_region()
683 bus_region.end = region + size - 1; in quirk_io_region()
684 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
692 * between 0x3b0->0x3bb or read 0x3d3
716 u32 class = pdev->class; in quirk_amd_dwc_class()
720 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_dwc_class()
722 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", in quirk_amd_dwc_class()
723 class, pdev->class); in quirk_amd_dwc_class()
734 * devices should use dwc3-haps driver. Change these devices' class code to
735 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
740 u32 class = pdev->class; in quirk_synopsys_haps()
742 switch (pdev->device) { in quirk_synopsys_haps()
746 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
747 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
748 class, pdev->class); in quirk_synopsys_haps()
795 base &= -size; in piix4_io_quirk()
796 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
821 base &= -size; in piix4_mem_quirk()
822 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
874 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
948 base &= ~(size-1); in ich6_lpc_generic_decode()
954 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
962 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
981 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
993 /* ICH7-10 has the same common LPC generic IO decode registers */
1025 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1042 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
1061 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1062 * back-to-back: Disable fast back-to-back on the secondary bus segment
1069 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1070 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1084 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1087 * TODO: When we have device-specific interrupt routers, this code will go
1097 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1109 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1121 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1129 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1139 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1151 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1152 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1153 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1160 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1164 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1165 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1166 dev->revision); in quirk_amd_8131_mmrbc()
1167 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1177 * -jgarzik
1187 d->irq = irq; in quirk_via_acpi()
1193 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1198 switch (dev->device) { in quirk_via_bridge()
1205 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1206 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1233 * quirk_via_vlink - VIA VLink IRQ number update
1248 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1251 new_irq = dev->irq; in quirk_via_vlink()
1258 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1259 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1284 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1327 * DreamWorks-provided workaround for Dunord I-3000 problem
1335 struct resource *r = &dev->resource[1]; in quirk_dunord()
1337 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1338 r->start = 0; in quirk_dunord()
1339 r->end = 0xffffff; in quirk_dunord()
1344 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1346 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1350 dev->transparent = 1; in quirk_transparent_bridge()
1385 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1399 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1410 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1430 pdev->class &= ~5; in quirk_svwks_csb5ide()
1437 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1447 pdev->class &= ~5; in quirk_ide_samemode()
1456 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1472 * This was originally an Alpha-specific thing, but it really fits here.
1473 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1477 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1490 * becomes necessary to do this tweak in two steps -- the chosen trigger
1491 * is either the Host bridge (preferred) or on-board VGA controller.
1504 * the DSDT and double-check that there is no code accessing the SMBus.
1510 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1511 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1512 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1513 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1519 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1520 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1521 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1523 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1527 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1531 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1532 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1536 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1537 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1538 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1542 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1549 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1554 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1555 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1556 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1560 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1565 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1566 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1567 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1572 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1573 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1580 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1584 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1585 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1586 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1590 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1591 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1592 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1596 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1597 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1598 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1601 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1604 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1605 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1610 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1616 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1617 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1621 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1773 dev->device = devid; in quirk_sis_503()
1783 * -- bjd
1790 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1791 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1824 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1830 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1833 switch (pdev->device) { in quirk_jmicron_ata()
1865 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1866 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1869 pdev->class = class >> 8; in quirk_jmicron_ata()
1894 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1895 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1896 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1909 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1913 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1918 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1925 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1933 dev->no_msi = 1; in quirk_no_msi()
1944 pdev->no_msi = 1; in quirk_pcie_mch()
1955 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1958 * break the PCI requirement for free-flowing writes and may lead to
1960 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1967 PROPERTY_ENTRY_BOOL("dma-can-stall"), in quirk_huawei_pcie_sva()
1971 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1974 pdev->pasid_no_tlp = 1; in quirk_huawei_pcie_sva()
1977 * Set the dma-can-stall property on ACPI platforms. Device tree in quirk_huawei_pcie_sva()
1980 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1981 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1993 * together on certain PXH-based systems.
1997 dev->no_msi = 1; in quirk_pcie_pxh()
2013 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
2039 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
2042 dev->d3hot_delay = delay; in quirk_d3hot_delay()
2043 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
2044 dev->d3hot_delay); in quirk_d3hot_delay()
2049 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
2050 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2056 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2074 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2089 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
2100 .ident = "ASUSTek Computer INC. M2N-LR",
2103 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2121 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2123 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2148 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2149 * 300641-004US, section 5.7.3.
2151 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2152 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2153 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2154 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2155 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2156 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2157 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2158 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2175 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2186 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2198 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2201 * Device 29 Func 5 Device IDs of IO-APIC
2237 /* Disable boot interrupts on HT-1000 */
2263 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2272 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2286 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2287 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2295 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2314 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2319 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2326 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2328 * Re-allocate the region if needed...
2332 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2334 if (r->start & 0x8) { in quirk_tc86c001_ide()
2335 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2336 r->start = 0; in quirk_tc86c001_ide()
2337 r->end = 0xf; in quirk_tc86c001_ide()
2349 * Re-allocate the regions to a 256-byte boundary if necessary.
2356 if (dev->revision >= 2) in quirk_plx_pci9050()
2361 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2362 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2364 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2365 r->start = 0; in quirk_plx_pci9050()
2366 r->end = 0xff; in quirk_plx_pci9050()
2385 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2386 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2398 switch (dev->device) { in quirk_netmos()
2401 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2402 dev->subsystem_device == 0x0299) in quirk_netmos()
2411 dev->device, num_parallel, num_serial); in quirk_netmos()
2412 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2413 (dev->class & 0xff); in quirk_netmos()
2426 switch (dev->device) { in quirk_e100_interrupt()
2451 * re-enable them when it's ready. in quirk_e100_interrupt()
2462 if (dev->pm_cap) { in quirk_e100_interrupt()
2463 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2517 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2524 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2533 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2542 u32 class = dev->class; in fixup_rev1_53c810()
2551 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2552 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2553 class, dev->class); in fixup_rev1_53c810()
2566 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2600 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2610 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2632 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2664 * DRBs - this is where we expose device 6.
2665 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2707 if (dev->subordinate) { in quirk_disable_msi()
2709 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2726 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2728 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2745 while (pos && ttl--) { in msi_ht_cap_enabled()
2783 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2799 while (pos && ttl--) { in ht_enable_msi_mapping()
2820 * The P5N32-SLI motherboards from Asus have a problem with MSI
2829 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2830 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2831 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2832 dev->no_msi = 1; in nvenet_msi_disable()
2840 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2845 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2850 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2940 while (pos && ttl--) { in ht_check_msi_mapping()
2968 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2970 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
3026 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
3027 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3028 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3063 while (pos && ttl--) { in ht_disable_msi_mapping()
3096 * a non-HyperTransport host bridge. Locate the host bridge. in __nv_msi_ht_cap_quirk()
3098 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3145 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3162 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3163 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3170 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3172 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3236 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3240 * tested), since currently there is no standard way to disable only MSI-X.
3247 dev->no_msi = 1; in quirk_al_msi_disable()
3248 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3256 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3263 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3280 * MMC controller - so the SDHCI driver never sees them.
3304 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3335 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3342 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3344 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3345 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3346 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3347 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3349 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3350 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3387 * This is a quirk for masking VT-d spec-defined errors to platform error
3389 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3390 * on the RAS config settings of the platform) when a VT-d fault happens.
3391 * The resulting SMI caused the system to hang.
3393 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3409 u32 class = dev->class; in fixup_ti816x_class()
3412 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3413 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3414 class, dev->class); in fixup_ti816x_class()
3425 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3440 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3476 /* Intel 5000 series memory controllers and ports 2-7 */
3491 /* Intel 5100 series memory controllers and ports 2-7 */
3518 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3524 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3533 * and the interrupt ends up -somewhere-.
3573 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3579 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3609 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3621 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3622 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3624 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3631 * DisINTx can be set but the interrupt status bit is non-functional.
3671 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3687 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3688 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3694 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3697 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3700 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3701 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3704 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3712 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3724 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3725 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3727 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3740 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3749 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3757 * The device will throw a Link Down error on AER-capable systems and
3792 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3793 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3797 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3798 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3808 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3809 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3827 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3828 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3829 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3830 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3877 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3908 * Following are device-specific reset methods which can be used to
3909 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3915 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3945 return -ENOMEM; in reset_ivb_igd()
3976 /* Device-specific reset method for Chelsio T4-based adapters */
3983 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3984 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3986 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3987 return -ENOTTY; in reset_chelsio_generic_dev()
4013 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
4014 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
4015 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
4017 * MSI-X state. in reset_chelsio_generic_dev()
4019 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
4021 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
4044 * FLR where config space reads from the device return -1. We seem to be
4061 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
4063 return -ENOTTY; in nvme_disable_and_flr()
4070 return -ENOTTY; in nvme_disable_and_flr()
4149 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4161 return -ENOTTY; in reset_hinic_vf_dev()
4167 return -ENOTTY; in reset_hinic_vf_dev()
4224 * These device-specific reset methods are here rather than in a driver
4232 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4233 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4234 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4235 (i->device == dev->device || in pci_dev_specific_reset()
4236 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4237 return i->reset(dev, probe); in pci_dev_specific_reset()
4240 return -ENOTTY; in pci_dev_specific_reset()
4245 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4246 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4263 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4264 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4322 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4332 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4357 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4362 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4367 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4368 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4372 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4373 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4374 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4375 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4376 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4393 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4406 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4441 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4449 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4454 u32 class = pdev->class; in quirk_tw686x_class()
4457 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4458 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4459 class, pdev->class); in quirk_tw686x_class()
4477 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4564 * If a non-compliant device generates a completion with a different
4566 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4570 * If the non-compliant device generates completions with zero attributes
4592 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4610 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4617 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4635 * AMD has indicated that the devices below do not support peer-to-peer
4638 * peer-to-peer between functions can claim to support a subset of ACS.
4666 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4667 return -ENODEV; in pci_quirk_amd_sb_acs()
4672 return -ENODEV; in pci_quirk_amd_sb_acs()
4681 return -ENODEV; in pci_quirk_amd_sb_acs()
4690 switch (dev->device) { in pci_quirk_cavium_acs_match()
4707 return -ENOTTY; in pci_quirk_cavium_acs()
4724 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4734 * But the implementation could block peer-to-peer transactions between them
4735 * and provide ACS-like functionality.
4742 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4748 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4760 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4775 /* Lynxpoint-H PCH */
4778 /* Lynxpoint-LP PCH */
4797 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4802 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4811 return -ENOTTY; in pci_quirk_intel_pch_acs()
4813 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4821 * These QCOM Root Ports do provide ACS-like features to disable peer
4825 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4851 return -ENOTTY; in pci_quirk_al_acs()
4855 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4856 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4876 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4877 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4885 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4889 * 0xa290-0xa29f PCI Express Root port #{0-16}
4890 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4896 * August 2017, Revision 002, Document#: 334660-002)[6]
4899 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4901 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4903 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4904 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4905 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4906 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4907 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4908 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4909 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4916 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4934 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4936 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4938 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4955 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4957 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4969 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4970 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4973 return -ENOTTY; in pci_quirk_rciep_acs()
4983 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4993 * multi-function devices, the hardware isolates the functions by
4994 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and
5002 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
5076 /* 82571 (Quads omitted due to non-ACS switch) */
5095 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5096 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5099 /* Cavium multi-function devices */
5103 /* APM X-Gene */
5114 /* Broadcom multi-function device */
5126 /* Zhaoxin multi-function devices */
5131 /* LX2xx0A : without security features + CAN-FD */
5135 /* LX2xx0C : security features + CAN-FD */
5147 /* LX2xx2A : without security features + CAN-FD */
5151 /* LX2xx2C : security features + CAN-FD */
5171 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5176 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5188 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
5189 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5192 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5193 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5194 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5195 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5196 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5197 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5203 return -ENOTTY; in pci_dev_specific_acs_enabled()
5215 /* Backbone Peer Non-Posted Disable */
5235 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5238 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5243 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5247 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5295 * if dev->external_facing || dev->untrusted
5300 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5309 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5322 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5324 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5326 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5336 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5352 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5354 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5356 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5392 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5393 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5394 (p->device == dev->device || in pci_dev_specific_enable_acs()
5395 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5396 p->enable_acs) { in pci_dev_specific_enable_acs()
5397 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5403 return -ENOTTY; in pci_dev_specific_enable_acs()
5413 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5414 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5415 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5416 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5417 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5418 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5424 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5442 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5462 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5475 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5477 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5479 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5481 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5484 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5494 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5495 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5496 state->cap.size = size; in quirk_intel_qat_vf_cap()
5497 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5505 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5522 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5534 if (dev->revision == 0x1) in quirk_no_flr_snet()
5541 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5546 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5549 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5564 pdev->ats_cap = 0; in quirk_no_ats()
5574 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5575 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5576 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5577 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5578 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5579 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5613 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5631 pdev->no_msi = 1; in quirk_fsl_no_msi()
5636 * Although not allowed by the spec, some multi-function devices have
5649 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5652 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5653 pdev->bus->number, in pci_create_device_link()
5654 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5655 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5660 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5668 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5701 * Create device link for GPUs with integrated Type-C UCSI controller
5728 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5739 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5741 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5752 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5754 * Item #36 - Downstream port applies ACS Source Validation to Completions
5767 * write, so we do config reads until we receive a non-Config Request Retry
5778 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5780 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5792 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5796 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5836 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5838 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5839 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5854 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5871 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
6017 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6018 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6061 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
6073 * 7.3.27, 7.3.29-7.3.31.
6079 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
6082 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6089 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
6095 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6115 if (!pdev->acs_cap) in pci_fixup_pericom_acs_store_forward()
6117 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); in pci_fixup_pericom_acs_store_forward()
6127 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); in pci_fixup_pericom_acs_store_forward()
6151 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()
6158 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
6175 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
6178 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
6231 dev->dpc_rp_log_size = 4; in dpc_log_size()
6274 pdev->d3cold_delay = 1000; in pci_fixup_d3cold_delay_1sec()