Lines Matching refs:dev
75 struct device *dev; in no_pci_devices() local
78 dev = bus_find_next_device(&pci_bus_type, NULL); in no_pci_devices()
79 no_devices = (dev == NULL); in no_pci_devices()
80 put_device(dev); in no_pci_devices()
88 static void release_pcibus_dev(struct device *dev) in release_pcibus_dev() argument
90 struct pci_bus *pci_bus = to_pci_bus(dev); in release_pcibus_dev()
132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) in decode_bar() argument
176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, in __pci_read_base() argument
187 if (!dev->mmio_always_on) { in __pci_read_base()
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); in __pci_read_base()
190 pci_write_config_word(dev, PCI_COMMAND, in __pci_read_base()
195 res->name = pci_name(dev); in __pci_read_base()
197 pci_read_config_dword(dev, pos, &l); in __pci_read_base()
198 pci_write_config_dword(dev, pos, l | mask); in __pci_read_base()
199 pci_read_config_dword(dev, pos, &sz); in __pci_read_base()
200 pci_write_config_dword(dev, pos, l); in __pci_read_base()
219 res->flags = decode_bar(dev, l); in __pci_read_base()
239 pci_read_config_dword(dev, pos + 4, &l); in __pci_read_base()
240 pci_write_config_dword(dev, pos + 4, ~0); in __pci_read_base()
241 pci_read_config_dword(dev, pos + 4, &sz); in __pci_read_base()
242 pci_write_config_dword(dev, pos + 4, l); in __pci_read_base()
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); in __pci_read_base()
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", in __pci_read_base()
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", in __pci_read_base()
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", in __pci_read_base()
287 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", in __pci_read_base()
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); in __pci_read_base()
321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) in pci_read_bases() argument
325 if (dev->non_compliant_bars) in pci_read_bases()
329 if (dev->is_virtfn) in pci_read_bases()
333 struct resource *res = &dev->resource[pos]; in pci_read_bases()
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); in pci_read_bases()
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
340 dev->rom_base_reg = rom; in pci_read_bases()
343 __pci_read_base(dev, pci_bar_mem32, res, rom); in pci_read_bases()
400 struct pci_dev *dev = child->self; in pci_read_bridge_io() local
408 if (dev->io_window_1k) { in pci_read_bridge_io()
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); in pci_read_bridge_io()
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); in pci_read_bridge_io()
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); in pci_read_bridge_io()
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); in pci_read_bridge_io()
433 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
434 pci_info(dev, " bridge window %pR\n", res); in pci_read_bridge_io()
440 struct pci_dev *dev = child->self; in pci_read_bridge_mmio() local
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio()
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio()
455 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
456 pci_info(dev, " bridge window %pR\n", res); in pci_read_bridge_mmio()
462 struct pci_dev *dev = child->self; in pci_read_bridge_mmio_pref() local
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio_pref()
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio_pref()
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); in pci_read_bridge_mmio_pref()
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); in pci_read_bridge_mmio_pref()
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", in pci_read_bridge_mmio_pref()
508 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
509 pci_info(dev, " bridge window %pR\n", res); in pci_read_bridge_mmio_pref()
515 struct pci_dev *dev = child->self; in pci_read_bridge_bases() local
522 pci_info(dev, "PCI bridge to %pR%s\n", in pci_read_bridge_bases()
524 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
534 if (dev->transparent) { in pci_read_bridge_bases()
539 pci_info(dev, " bridge window %pR (subtractive decode)\n", in pci_read_bridge_bases()
568 static void pci_release_host_bridge_dev(struct device *dev) in pci_release_host_bridge_dev() argument
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); in pci_release_host_bridge_dev()
600 device_initialize(&bridge->dev); in pci_init_host_bridge()
612 bridge->dev.release = pci_release_host_bridge_dev; in pci_alloc_host_bridge()
623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, in devm_pci_alloc_host_bridge() argument
633 bridge->dev.parent = dev; in devm_pci_alloc_host_bridge()
635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, in devm_pci_alloc_host_bridge()
640 ret = devm_of_pci_bridge_init(dev, bridge); in devm_pci_alloc_host_bridge()
650 put_device(&bridge->dev); in pci_free_host_bridge()
871 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
877 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
882 struct device *parent = bridge->dev.parent; in pci_register_host_bridge()
915 dev_dbg(&b->dev, "bus already known\n"); in pci_register_host_bridge()
920 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), in pci_register_host_bridge()
929 err = device_add(&bridge->dev); in pci_register_host_bridge()
931 put_device(&bridge->dev); in pci_register_host_bridge()
934 bus->bridge = get_device(&bridge->dev); in pci_register_host_bridge()
938 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && in pci_register_host_bridge()
945 bus->dev.class = &pcibus_class; in pci_register_host_bridge()
946 bus->dev.parent = bus->bridge; in pci_register_host_bridge()
948 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); in pci_register_host_bridge()
949 name = dev_name(&bus->dev); in pci_register_host_bridge()
951 err = device_register(&bus->dev); in pci_register_host_bridge()
960 dev_err(&bus->dev, "failed to add bus: %d\n", err); in pci_register_host_bridge()
972 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); in pci_register_host_bridge()
1023 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); in pci_register_host_bridge()
1033 put_device(&bridge->dev); in pci_register_host_bridge()
1034 device_del(&bridge->dev); in pci_register_host_bridge()
1110 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
1111 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
1119 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
1124 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
1125 child->dev.parent = child->bridge; in pci_alloc_child_bus()
1148 ret = device_register(&child->dev); in pci_alloc_child_bus()
1156 dev_err(&child->dev, "failed to add bus: %d\n", ret); in pci_alloc_child_bus()
1165 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, in pci_add_new_bus() argument
1170 child = pci_alloc_child_bus(parent, dev, busnr); in pci_add_new_bus()
1204 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) in pci_ea_fixed_busnrs() argument
1210 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) in pci_ea_fixed_busnrs()
1214 ea = pci_find_capability(dev, PCI_CAP_ID_EA); in pci_ea_fixed_busnrs()
1219 pci_read_config_dword(dev, offset, &dw); in pci_ea_fixed_busnrs()
1253 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, in pci_scan_bridge_extend() argument
1258 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge_extend()
1271 pm_runtime_get_sync(&dev->dev); in pci_scan_bridge_extend()
1273 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); in pci_scan_bridge_extend()
1278 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge_extend()
1282 pci_warn(dev, "Primary bus is hard wired to 0\n"); in pci_scan_bridge_extend()
1290 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge_extend()
1299 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); in pci_scan_bridge_extend()
1300 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, in pci_scan_bridge_extend()
1303 pci_enable_crs(dev); in pci_scan_bridge_extend()
1324 child = pci_add_new_bus(bus, dev, secondary); in pci_scan_bridge_extend()
1335 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", in pci_scan_bridge_extend()
1358 pci_write_config_dword(dev, PCI_PRIMARY_BUS, in pci_scan_bridge_extend()
1364 pci_write_config_word(dev, PCI_STATUS, 0xffff); in pci_scan_bridge_extend()
1367 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); in pci_scan_bridge_extend()
1380 child = pci_add_new_bus(bus, dev, next_busnr); in pci_scan_bridge_extend()
1405 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); in pci_scan_bridge_extend()
1452 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); in pci_scan_bridge_extend()
1465 …dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", in pci_scan_bridge_extend()
1473 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); in pci_scan_bridge_extend()
1475 pm_runtime_put(&dev->dev); in pci_scan_bridge_extend()
1499 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) in pci_scan_bridge() argument
1501 return pci_scan_bridge_extend(bus, dev, max, 0, pass); in pci_scan_bridge()
1509 static void pci_read_irq(struct pci_dev *dev) in pci_read_irq() argument
1514 if (dev->is_virtfn) { in pci_read_irq()
1515 dev->pin = 0; in pci_read_irq()
1516 dev->irq = 0; in pci_read_irq()
1520 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); in pci_read_irq()
1521 dev->pin = irq; in pci_read_irq()
1523 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in pci_read_irq()
1524 dev->irq = irq; in pci_read_irq()
1593 static void set_pcie_thunderbolt(struct pci_dev *dev) in set_pcie_thunderbolt() argument
1598 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); in set_pcie_thunderbolt()
1600 dev->is_thunderbolt = 1; in set_pcie_thunderbolt()
1603 static void set_pcie_untrusted(struct pci_dev *dev) in set_pcie_untrusted() argument
1611 parent = pci_upstream_bridge(dev); in set_pcie_untrusted()
1613 dev->untrusted = true; in set_pcie_untrusted()
1616 static void pci_set_removable(struct pci_dev *dev) in pci_set_removable() argument
1618 struct pci_dev *parent = pci_upstream_bridge(dev); in pci_set_removable()
1632 (parent->external_facing || dev_is_removable(&parent->dev))) in pci_set_removable()
1633 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); in pci_set_removable()
1652 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) in pci_ext_cfg_is_aliased() argument
1658 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); in pci_ext_cfg_is_aliased()
1662 ret = pci_read_config_dword(dev, pos, &tmp); in pci_ext_cfg_is_aliased()
1684 static int pci_cfg_space_size_ext(struct pci_dev *dev) in pci_cfg_space_size_ext() argument
1689 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) in pci_cfg_space_size_ext()
1691 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) in pci_cfg_space_size_ext()
1697 int pci_cfg_space_size(struct pci_dev *dev) in pci_cfg_space_size() argument
1714 if (dev->is_virtfn) in pci_cfg_space_size()
1718 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_cfg_space_size()
1721 class = dev->class >> 8; in pci_cfg_space_size()
1723 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1725 if (pci_is_pcie(dev)) in pci_cfg_space_size()
1726 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1728 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pci_cfg_space_size()
1732 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); in pci_cfg_space_size()
1734 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1739 static u32 pci_class(struct pci_dev *dev) in pci_class() argument
1744 if (dev->is_virtfn) in pci_class()
1745 return dev->physfn->sriov->class; in pci_class()
1747 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); in pci_class()
1751 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) in pci_subsystem_ids() argument
1754 if (dev->is_virtfn) { in pci_subsystem_ids()
1755 *vendor = dev->physfn->sriov->subsystem_vendor; in pci_subsystem_ids()
1756 *device = dev->physfn->sriov->subsystem_device; in pci_subsystem_ids()
1760 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); in pci_subsystem_ids()
1761 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); in pci_subsystem_ids()
1764 static u8 pci_hdr_type(struct pci_dev *dev) in pci_hdr_type() argument
1769 if (dev->is_virtfn) in pci_hdr_type()
1770 return dev->physfn->sriov->hdr_type; in pci_hdr_type()
1772 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); in pci_hdr_type()
1785 static int pci_intx_mask_broken(struct pci_dev *dev) in pci_intx_mask_broken() argument
1789 pci_read_config_word(dev, PCI_COMMAND, &orig); in pci_intx_mask_broken()
1791 pci_write_config_word(dev, PCI_COMMAND, toggle); in pci_intx_mask_broken()
1792 pci_read_config_word(dev, PCI_COMMAND, &new); in pci_intx_mask_broken()
1794 pci_write_config_word(dev, PCI_COMMAND, orig); in pci_intx_mask_broken()
1830 int pci_setup_device(struct pci_dev *dev) in pci_setup_device() argument
1839 hdr_type = pci_hdr_type(dev); in pci_setup_device()
1841 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1842 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1843 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1844 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1845 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1846 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1847 set_pcie_port_type(dev); in pci_setup_device()
1849 err = pci_set_of_node(dev); in pci_setup_device()
1852 pci_set_acpi_fwnode(dev); in pci_setup_device()
1854 pci_dev_assign_slot(dev); in pci_setup_device()
1860 dev->dma_mask = 0xffffffff; in pci_setup_device()
1862 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1863 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1864 PCI_FUNC(dev->devfn)); in pci_setup_device()
1866 class = pci_class(dev); in pci_setup_device()
1868 dev->revision = class & 0xff; in pci_setup_device()
1869 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1872 early_dump_pci_device(dev); in pci_setup_device()
1875 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1878 set_pcie_thunderbolt(dev); in pci_setup_device()
1880 set_pcie_untrusted(dev); in pci_setup_device()
1883 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1886 pci_fixup_device(pci_fixup_early, dev); in pci_setup_device()
1888 pci_set_removable(dev); in pci_setup_device()
1890 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", in pci_setup_device()
1891 dev->vendor, dev->device, dev->hdr_type, dev->class); in pci_setup_device()
1894 class = dev->class >> 8; in pci_setup_device()
1896 if (dev->non_compliant_bars && !dev->mmio_always_on) { in pci_setup_device()
1897 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_setup_device()
1899 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1902 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_setup_device()
1906 dev->broken_intx_masking = pci_intx_mask_broken(dev); in pci_setup_device()
1908 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1912 pci_read_irq(dev); in pci_setup_device()
1913 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); in pci_setup_device()
1915 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); in pci_setup_device()
1925 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); in pci_setup_device()
1929 res = &dev->resource[0]; in pci_setup_device()
1931 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1932 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", in pci_setup_device()
1936 res = &dev->resource[1]; in pci_setup_device()
1938 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1939 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", in pci_setup_device()
1945 res = &dev->resource[2]; in pci_setup_device()
1947 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1948 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", in pci_setup_device()
1952 res = &dev->resource[3]; in pci_setup_device()
1954 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1955 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", in pci_setup_device()
1967 pci_read_irq(dev); in pci_setup_device()
1968 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
1969 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); in pci_setup_device()
1970 pci_read_bridge_windows(dev); in pci_setup_device()
1971 set_pcie_hotplug_bridge(dev); in pci_setup_device()
1972 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); in pci_setup_device()
1974 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1975 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
1982 pci_read_irq(dev); in pci_setup_device()
1983 pci_read_bases(dev, 1, 0); in pci_setup_device()
1984 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1985 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1989 pci_err(dev, "unknown header type %02x, ignoring device\n", in pci_setup_device()
1990 dev->hdr_type); in pci_setup_device()
1991 pci_release_of_node(dev); in pci_setup_device()
1995 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", in pci_setup_device()
1996 dev->class, dev->hdr_type); in pci_setup_device()
1997 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
2004 static void pci_configure_mps(struct pci_dev *dev) in pci_configure_mps() argument
2006 struct pci_dev *bridge = pci_upstream_bridge(dev); in pci_configure_mps()
2009 if (!pci_is_pcie(dev)) in pci_configure_mps()
2013 if (dev->is_virtfn) in pci_configure_mps()
2020 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { in pci_configure_mps()
2024 mps = 128 << dev->pcie_mpss; in pci_configure_mps()
2025 rc = pcie_set_mps(dev, mps); in pci_configure_mps()
2027 …pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and repor… in pci_configure_mps()
2036 mps = pcie_get_mps(dev); in pci_configure_mps()
2043 …pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_sa… in pci_configure_mps()
2055 mpss = 128 << dev->pcie_mpss; in pci_configure_mps()
2058 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", in pci_configure_mps()
2063 rc = pcie_set_mps(dev, p_mps); in pci_configure_mps()
2065 …pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and repor… in pci_configure_mps()
2070 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", in pci_configure_mps()
2074 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) in pci_configure_extended_tags() argument
2081 if (!pci_is_pcie(dev)) in pci_configure_extended_tags()
2084 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); in pci_configure_extended_tags()
2091 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); in pci_configure_extended_tags()
2095 host = pci_find_host_bridge(dev->bus); in pci_configure_extended_tags()
2105 pci_info(dev, "disabling Extended Tags\n"); in pci_configure_extended_tags()
2106 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, in pci_configure_extended_tags()
2113 pci_info(dev, "enabling Extended Tags\n"); in pci_configure_extended_tags()
2114 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, in pci_configure_extended_tags()
2126 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) in pcie_relaxed_ordering_enabled() argument
2130 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); in pcie_relaxed_ordering_enabled()
2136 static void pci_configure_relaxed_ordering(struct pci_dev *dev) in pci_configure_relaxed_ordering() argument
2141 if (dev->is_virtfn) in pci_configure_relaxed_ordering()
2144 if (!pcie_relaxed_ordering_enabled(dev)) in pci_configure_relaxed_ordering()
2151 root = pcie_find_root_port(dev); in pci_configure_relaxed_ordering()
2156 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, in pci_configure_relaxed_ordering()
2158 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); in pci_configure_relaxed_ordering()
2162 static void pci_configure_ltr(struct pci_dev *dev) in pci_configure_ltr() argument
2165 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); in pci_configure_ltr()
2169 if (!pci_is_pcie(dev)) in pci_configure_ltr()
2173 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); in pci_configure_ltr()
2175 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); in pci_configure_ltr()
2179 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); in pci_configure_ltr()
2181 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { in pci_configure_ltr()
2182 dev->ltr_path = 1; in pci_configure_ltr()
2186 bridge = pci_upstream_bridge(dev); in pci_configure_ltr()
2188 dev->ltr_path = 1; in pci_configure_ltr()
2201 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { in pci_configure_ltr()
2202 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, in pci_configure_ltr()
2204 dev->ltr_path = 1; in pci_configure_ltr()
2213 bridge = pci_upstream_bridge(dev); in pci_configure_ltr()
2215 pci_bridge_reconfigure_ltr(dev); in pci_configure_ltr()
2216 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, in pci_configure_ltr()
2218 dev->ltr_path = 1; in pci_configure_ltr()
2223 static void pci_configure_eetlp_prefix(struct pci_dev *dev) in pci_configure_eetlp_prefix() argument
2230 if (!pci_is_pcie(dev)) in pci_configure_eetlp_prefix()
2233 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); in pci_configure_eetlp_prefix()
2237 pcie_type = pci_pcie_type(dev); in pci_configure_eetlp_prefix()
2240 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2242 bridge = pci_upstream_bridge(dev); in pci_configure_eetlp_prefix()
2244 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2249 static void pci_configure_serr(struct pci_dev *dev) in pci_configure_serr() argument
2253 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_configure_serr()
2259 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); in pci_configure_serr()
2262 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); in pci_configure_serr()
2267 static void pci_configure_device(struct pci_dev *dev) in pci_configure_device() argument
2269 pci_configure_mps(dev); in pci_configure_device()
2270 pci_configure_extended_tags(dev, NULL); in pci_configure_device()
2271 pci_configure_relaxed_ordering(dev); in pci_configure_device()
2272 pci_configure_ltr(dev); in pci_configure_device()
2273 pci_configure_eetlp_prefix(dev); in pci_configure_device()
2274 pci_configure_serr(dev); in pci_configure_device()
2276 pci_acpi_program_hp_params(dev); in pci_configure_device()
2279 static void pci_release_capabilities(struct pci_dev *dev) in pci_release_capabilities() argument
2281 pci_aer_exit(dev); in pci_release_capabilities()
2282 pci_rcec_exit(dev); in pci_release_capabilities()
2283 pci_iov_release(dev); in pci_release_capabilities()
2284 pci_free_cap_save_buffers(dev); in pci_release_capabilities()
2295 static void pci_release_dev(struct device *dev) in pci_release_dev() argument
2299 pci_dev = to_pci_dev(dev); in pci_release_dev()
2306 dev_dbg(dev, "device released\n"); in pci_release_dev()
2312 struct pci_dev *dev; in pci_alloc_dev() local
2314 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); in pci_alloc_dev()
2315 if (!dev) in pci_alloc_dev()
2318 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
2319 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
2320 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
2321 dev->driver_exclusive_resource = (struct resource) { in pci_alloc_dev()
2327 spin_lock_init(&dev->pcie_cap_lock); in pci_alloc_dev()
2329 raw_spin_lock_init(&dev->msi_lock); in pci_alloc_dev()
2331 return dev; in pci_alloc_dev()
2426 struct pci_dev *dev; in pci_scan_device() local
2432 dev = pci_alloc_dev(bus); in pci_scan_device()
2433 if (!dev) in pci_scan_device()
2436 dev->devfn = devfn; in pci_scan_device()
2437 dev->vendor = l & 0xffff; in pci_scan_device()
2438 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
2440 if (pci_setup_device(dev)) { in pci_scan_device()
2441 pci_bus_put(dev->bus); in pci_scan_device()
2442 kfree(dev); in pci_scan_device()
2446 return dev; in pci_scan_device()
2449 void pcie_report_downtraining(struct pci_dev *dev) in pcie_report_downtraining() argument
2451 if (!pci_is_pcie(dev)) in pcie_report_downtraining()
2455 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && in pcie_report_downtraining()
2456 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && in pcie_report_downtraining()
2457 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) in pcie_report_downtraining()
2461 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) in pcie_report_downtraining()
2465 __pcie_print_link_status(dev, false); in pcie_report_downtraining()
2468 static void pci_init_capabilities(struct pci_dev *dev) in pci_init_capabilities() argument
2470 pci_ea_init(dev); /* Enhanced Allocation */ in pci_init_capabilities()
2471 pci_msi_init(dev); /* Disable MSI */ in pci_init_capabilities()
2472 pci_msix_init(dev); /* Disable MSI-X */ in pci_init_capabilities()
2475 pci_allocate_cap_save_buffers(dev); in pci_init_capabilities()
2477 pci_pm_init(dev); /* Power Management */ in pci_init_capabilities()
2478 pci_vpd_init(dev); /* Vital Product Data */ in pci_init_capabilities()
2479 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ in pci_init_capabilities()
2480 pci_iov_init(dev); /* Single Root I/O Virtualization */ in pci_init_capabilities()
2481 pci_ats_init(dev); /* Address Translation Services */ in pci_init_capabilities()
2482 pci_pri_init(dev); /* Page Request Interface */ in pci_init_capabilities()
2483 pci_pasid_init(dev); /* Process Address Space ID */ in pci_init_capabilities()
2484 pci_acs_init(dev); /* Access Control Services */ in pci_init_capabilities()
2485 pci_ptm_init(dev); /* Precision Time Measurement */ in pci_init_capabilities()
2486 pci_aer_init(dev); /* Advanced Error Reporting */ in pci_init_capabilities()
2487 pci_dpc_init(dev); /* Downstream Port Containment */ in pci_init_capabilities()
2488 pci_rcec_init(dev); /* Root Complex Event Collector */ in pci_init_capabilities()
2489 pci_doe_init(dev); /* Data Object Exchange */ in pci_init_capabilities()
2491 pcie_report_downtraining(dev); in pci_init_capabilities()
2492 pci_init_reset_methods(dev); in pci_init_capabilities()
2500 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) in pci_dev_msi_domain() argument
2508 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
2516 d = pci_msi_get_device_domain(dev); in pci_dev_msi_domain()
2523 static void pci_set_msi_domain(struct pci_dev *dev) in pci_set_msi_domain() argument
2532 d = pci_dev_msi_domain(dev); in pci_set_msi_domain()
2534 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
2536 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
2539 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) in pci_device_add() argument
2543 pci_configure_device(dev); in pci_device_add()
2545 device_initialize(&dev->dev); in pci_device_add()
2546 dev->dev.release = pci_release_dev; in pci_device_add()
2548 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
2549 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
2550 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
2551 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
2553 dma_set_max_seg_size(&dev->dev, 65536); in pci_device_add()
2554 dma_set_seg_boundary(&dev->dev, 0xffffffff); in pci_device_add()
2556 pcie_failed_link_retrain(dev); in pci_device_add()
2559 pci_fixup_device(pci_fixup_header, dev); in pci_device_add()
2561 pci_reassigndev_resource_alignment(dev); in pci_device_add()
2563 dev->state_saved = false; in pci_device_add()
2565 pci_init_capabilities(dev); in pci_device_add()
2572 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
2575 ret = pcibios_device_add(dev); in pci_device_add()
2579 pci_set_msi_domain(dev); in pci_device_add()
2582 dev->match_driver = false; in pci_device_add()
2583 ret = device_add(&dev->dev); in pci_device_add()
2589 struct pci_dev *dev; in pci_scan_single_device() local
2591 dev = pci_get_slot(bus, devfn); in pci_scan_single_device()
2592 if (dev) { in pci_scan_single_device()
2593 pci_dev_put(dev); in pci_scan_single_device()
2594 return dev; in pci_scan_single_device()
2597 dev = pci_scan_device(bus, devfn); in pci_scan_single_device()
2598 if (!dev) in pci_scan_single_device()
2601 pci_device_add(dev, bus); in pci_scan_single_device()
2603 return dev; in pci_scan_single_device()
2607 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) in next_ari_fn() argument
2613 if (!dev) in next_ari_fn()
2616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); in next_ari_fn()
2620 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); in next_ari_fn()
2628 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) in next_fn() argument
2631 return next_ari_fn(bus, dev, fn); in next_fn()
2636 if (dev && !dev->multifunction) in next_fn()
2677 struct pci_dev *dev; in pci_scan_slot() local
2684 dev = pci_scan_single_device(bus, devfn + fn); in pci_scan_slot()
2685 if (dev) { in pci_scan_slot()
2686 if (!pci_dev_is_added(dev)) in pci_scan_slot()
2689 dev->multifunction = 1; in pci_scan_slot()
2699 fn = next_fn(bus, dev, fn); in pci_scan_slot()
2710 static int pcie_find_smpss(struct pci_dev *dev, void *data) in pcie_find_smpss() argument
2714 if (!pci_is_pcie(dev)) in pcie_find_smpss()
2732 if (dev->is_hotplug_bridge && in pcie_find_smpss()
2733 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pcie_find_smpss()
2736 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
2737 *smpss = dev->pcie_mpss; in pcie_find_smpss()
2742 static void pcie_write_mps(struct pci_dev *dev, int mps) in pcie_write_mps() argument
2747 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
2749 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && in pcie_write_mps()
2750 dev->bus->self) in pcie_write_mps()
2765 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
2768 rc = pcie_set_mps(dev, mps); in pcie_write_mps()
2770 pci_err(dev, "Failed attempting to set the MPS\n"); in pcie_write_mps()
2773 static void pcie_write_mrrs(struct pci_dev *dev) in pcie_write_mrrs() argument
2790 mrrs = pcie_get_mps(dev); in pcie_write_mrrs()
2798 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { in pcie_write_mrrs()
2799 rc = pcie_set_readrq(dev, mrrs); in pcie_write_mrrs()
2803 pci_warn(dev, "Failed attempting to set the MRRS\n"); in pcie_write_mrrs()
2808 …pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, tr… in pcie_write_mrrs()
2811 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) in pcie_bus_configure_set() argument
2815 if (!pci_is_pcie(dev)) in pcie_bus_configure_set()
2823 orig_mps = pcie_get_mps(dev); in pcie_bus_configure_set()
2825 pcie_write_mps(dev, mps); in pcie_bus_configure_set()
2826 pcie_write_mrrs(dev); in pcie_bus_configure_set()
2828 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", in pcie_bus_configure_set()
2829 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
2830 orig_mps, pcie_get_readrq(dev)); in pcie_bus_configure_set()
2897 struct pci_dev *dev; in pci_scan_child_bus_extend() local
2899 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus_extend()
2914 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus_extend()
2924 for_each_pci_bridge(dev, bus) { in pci_scan_child_bus_extend()
2925 if (dev->is_hotplug_bridge) in pci_scan_child_bus_extend()
2936 for_each_pci_bridge(dev, bus) { in pci_scan_child_bus_extend()
2938 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); in pci_scan_child_bus_extend()
2950 for_each_pci_bridge(dev, bus) { in pci_scan_child_bus_extend()
2961 } else if (dev->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2971 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); in pci_scan_child_bus_extend()
2992 dev_dbg(&bus->dev, "%pR extended by %#02x\n", in pci_scan_child_bus_extend()
3004 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus_extend()
3051 bridge->dev.parent = parent; in pci_create_root_bus()
3065 put_device(&bridge->dev); in pci_create_root_bus()
3077 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in pci_host_probe()
3122 dev_info(&b->dev, in pci_bus_insert_busn_res()
3142 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", in pci_bus_update_busn_res_end()
3160 dev_info(&b->dev, "busn_res: %pR %s released\n", in pci_bus_release_busn_res()
3189 dev_info(&b->dev, in pci_scan_root_bus_bridge()
3223 dev_info(&b->dev, in pci_scan_root_bus()
3344 int pci_hp_add_bridge(struct pci_dev *dev) in pci_hp_add_bridge() argument
3346 struct pci_bus *parent = dev->bus; in pci_hp_add_bridge()
3356 pci_err(dev, "No bus number available for hot-added bridge\n"); in pci_hp_add_bridge()
3361 busnr = pci_scan_bridge(parent, dev, busnr, 0); in pci_hp_add_bridge()
3370 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); in pci_hp_add_bridge()
3372 if (!dev->subordinate) in pci_hp_add_bridge()