Lines Matching +full:iov +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
51 if (r->domain_nr == domain_nr) in get_pci_domain_busn_res()
52 return &r->res; in get_pci_domain_busn_res()
58 r->domain_nr = domain_nr; in get_pci_domain_busn_res()
59 r->res.start = 0; in get_pci_domain_busn_res()
60 r->res.end = 0xff; in get_pci_domain_busn_res()
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; in get_pci_domain_busn_res()
63 list_add_tail(&r->list, &pci_domain_busn_res_list); in get_pci_domain_busn_res()
65 return &r->res; in get_pci_domain_busn_res()
92 put_device(pci_bus->bridge); in release_pcibus_dev()
120 size = size & ~(size-1); in pci_size()
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) in pci_size()
153 /* 1M mem BAR treated as 32-bit BAR */ in decode_bar()
159 /* mem unknown type treated as 32-bit BAR */ in decode_bar()
168 * __pci_read_base - Read a PCI BAR
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
187 if (!dev->mmio_always_on) { in __pci_read_base()
195 res->name = pci_name(dev); in __pci_read_base()
219 res->flags = decode_bar(dev, l); in __pci_read_base()
220 res->flags |= IORESOURCE_SIZEALIGN; in __pci_read_base()
221 if (res->flags & IORESOURCE_IO) { in __pci_read_base()
232 res->flags |= IORESOURCE_ROM_ENABLE; in __pci_read_base()
238 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
262 if (res->flags & IORESOURCE_MEM_64) { in __pci_read_base()
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; in __pci_read_base()
266 res->start = 0; in __pci_read_base()
267 res->end = 0; in __pci_read_base()
274 /* Above 32-bit boundary; try to reallocate */ in __pci_read_base()
275 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
276 res->start = 0; in __pci_read_base()
277 res->end = sz64 - 1; in __pci_read_base()
285 region.end = l64 + sz64 - 1; in __pci_read_base()
287 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
302 res->flags |= IORESOURCE_UNSET; in __pci_read_base()
303 res->start = 0; in __pci_read_base()
304 res->end = region.end - region.start; in __pci_read_base()
313 res->flags = 0; in __pci_read_base()
315 if (res->flags) in __pci_read_base()
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; in __pci_read_base()
325 if (dev->non_compliant_bars) in pci_read_bases()
329 if (dev->is_virtfn) in pci_read_bases()
333 struct resource *res = &dev->resource[pos]; in pci_read_bases()
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
340 dev->rom_base_reg = rom; in pci_read_bases()
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | in pci_read_bases()
359 bridge->io_window = 1; in pci_read_bridge_windows()
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) in pci_read_bridge_windows()
379 bridge->pref_window = 1; in pci_read_bridge_windows()
384 * Bridge claims to have a 64-bit prefetchable memory in pci_read_bridge_windows()
394 bridge->pref_64_window = 1; in pci_read_bridge_windows()
400 struct pci_dev *dev = child->self; in pci_read_bridge_io()
408 if (dev->io_window_1k) { in pci_read_bridge_io()
414 res = child->resource[0]; in pci_read_bridge_io()
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; in pci_read_bridge_io()
432 region.end = limit + io_granularity - 1; in pci_read_bridge_io()
433 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
440 struct pci_dev *dev = child->self; in pci_read_bridge_mmio()
446 res = child->resource[1]; in pci_read_bridge_mmio()
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; in pci_read_bridge_mmio()
455 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
462 struct pci_dev *dev = child->self; in pci_read_bridge_mmio_pref()
469 res = child->resource[2]; in pci_read_bridge_mmio_pref()
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | in pci_read_bridge_mmio_pref()
504 if (res->flags & PCI_PREF_RANGE_TYPE_64) in pci_read_bridge_mmio_pref()
505 res->flags |= IORESOURCE_MEM_64; in pci_read_bridge_mmio_pref()
508 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
515 struct pci_dev *dev = child->self; in pci_read_bridge_bases()
523 &child->busn_res, in pci_read_bridge_bases()
524 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
534 if (dev->transparent) { in pci_read_bridge_bases()
535 pci_bus_for_each_resource(child->parent, res) { in pci_read_bridge_bases()
536 if (res && res->flags) { in pci_read_bridge_bases()
554 INIT_LIST_HEAD(&b->node); in pci_alloc_bus()
555 INIT_LIST_HEAD(&b->children); in pci_alloc_bus()
556 INIT_LIST_HEAD(&b->devices); in pci_alloc_bus()
557 INIT_LIST_HEAD(&b->slots); in pci_alloc_bus()
558 INIT_LIST_HEAD(&b->resources); in pci_alloc_bus()
559 b->max_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; in pci_alloc_bus()
563 b->domain_nr = parent->domain_nr; in pci_alloc_bus()
572 if (bridge->release_fn) in pci_release_host_bridge_dev()
573 bridge->release_fn(bridge); in pci_release_host_bridge_dev()
575 pci_free_resource_list(&bridge->windows); in pci_release_host_bridge_dev()
576 pci_free_resource_list(&bridge->dma_ranges); in pci_release_host_bridge_dev()
582 INIT_LIST_HEAD(&bridge->windows); in pci_init_host_bridge()
583 INIT_LIST_HEAD(&bridge->dma_ranges); in pci_init_host_bridge()
591 bridge->native_aer = 1; in pci_init_host_bridge()
592 bridge->native_pcie_hotplug = 1; in pci_init_host_bridge()
593 bridge->native_shpc_hotplug = 1; in pci_init_host_bridge()
594 bridge->native_pme = 1; in pci_init_host_bridge()
595 bridge->native_ltr = 1; in pci_init_host_bridge()
596 bridge->native_dpc = 1; in pci_init_host_bridge()
597 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; in pci_init_host_bridge()
598 bridge->native_cxl_error = 1; in pci_init_host_bridge()
600 device_initialize(&bridge->dev); in pci_init_host_bridge()
612 bridge->dev.release = pci_release_host_bridge_dev; in pci_alloc_host_bridge()
633 bridge->dev.parent = dev; in devm_pci_alloc_host_bridge()
650 put_device(&bridge->dev); in pci_free_host_bridge()
701 "66 MHz PCI-X", /* 0x02 */ in pci_speed_string()
702 "100 MHz PCI-X", /* 0x03 */ in pci_speed_string()
703 "133 MHz PCI-X", /* 0x04 */ in pci_speed_string()
708 "66 MHz PCI-X 266", /* 0x09 */ in pci_speed_string()
709 "100 MHz PCI-X 266", /* 0x0a */ in pci_speed_string()
710 "133 MHz PCI-X 266", /* 0x0b */ in pci_speed_string()
716 "66 MHz PCI-X 533", /* 0x11 */ in pci_speed_string()
717 "100 MHz PCI-X 533", /* 0x12 */ in pci_speed_string()
718 "133 MHz PCI-X 533", /* 0x13 */ in pci_speed_string()
735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; in pcie_update_link_speed()
772 struct pci_dev *bridge = bus->self; in pci_set_bus_speed()
782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); in pci_set_bus_speed()
785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); in pci_set_bus_speed()
809 bus->max_bus_speed = max; in pci_set_bus_speed()
810 bus->cur_bus_speed = pcix_bus_speed[ in pci_set_bus_speed()
821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; in pci_set_bus_speed()
833 d = dev_get_msi_domain(bus->bridge); in pci_host_bridge_msi_domain()
866 * created by an SR-IOV device. Walk up to the first bridge device in pci_set_bus_msi_domain()
869 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { in pci_set_bus_msi_domain()
870 if (b->self) in pci_set_bus_msi_domain()
871 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
877 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
882 struct device *parent = bridge->dev.parent; in pci_register_host_bridge()
894 return -ENOMEM; in pci_register_host_bridge()
896 bridge->bus = bus; in pci_register_host_bridge()
898 bus->sysdata = bridge->sysdata; in pci_register_host_bridge()
899 bus->ops = bridge->ops; in pci_register_host_bridge()
900 bus->number = bus->busn_res.start = bridge->busnr; in pci_register_host_bridge()
902 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) in pci_register_host_bridge()
903 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); in pci_register_host_bridge()
905 bus->domain_nr = bridge->domain_nr; in pci_register_host_bridge()
906 if (bus->domain_nr < 0) { in pci_register_host_bridge()
907 err = bus->domain_nr; in pci_register_host_bridge()
912 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); in pci_register_host_bridge()
915 dev_dbg(&b->dev, "bus already known\n"); in pci_register_host_bridge()
916 err = -EEXIST; in pci_register_host_bridge()
920 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), in pci_register_host_bridge()
921 bridge->busnr); in pci_register_host_bridge()
928 list_splice_init(&bridge->windows, &resources); in pci_register_host_bridge()
929 err = device_add(&bridge->dev); in pci_register_host_bridge()
931 put_device(&bridge->dev); in pci_register_host_bridge()
934 bus->bridge = get_device(&bridge->dev); in pci_register_host_bridge()
935 device_enable_async_suspend(bus->bridge); in pci_register_host_bridge()
938 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && in pci_register_host_bridge()
940 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in pci_register_host_bridge()
943 set_dev_node(bus->bridge, pcibus_to_node(bus)); in pci_register_host_bridge()
945 bus->dev.class = &pcibus_class; in pci_register_host_bridge()
946 bus->dev.parent = bus->bridge; in pci_register_host_bridge()
948 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); in pci_register_host_bridge()
949 name = dev_name(&bus->dev); in pci_register_host_bridge()
951 err = device_register(&bus->dev); in pci_register_host_bridge()
957 if (bus->ops->add_bus) { in pci_register_host_bridge()
958 err = bus->ops->add_bus(bus); in pci_register_host_bridge()
960 dev_err(&bus->dev, "failed to add bus: %d\n", err); in pci_register_host_bridge()
972 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); in pci_register_host_bridge()
976 if (list_is_last(&window->node, &resources)) in pci_register_host_bridge()
980 offset = window->offset; in pci_register_host_bridge()
981 res = window->res; in pci_register_host_bridge()
982 next_offset = next->offset; in pci_register_host_bridge()
983 next_res = next->res; in pci_register_host_bridge()
985 if (res->flags != next_res->flags || offset != next_offset) in pci_register_host_bridge()
988 if (res->end + 1 == next_res->start) { in pci_register_host_bridge()
989 next_res->start = res->start; in pci_register_host_bridge()
990 res->flags = res->start = res->end = 0; in pci_register_host_bridge()
996 offset = window->offset; in pci_register_host_bridge()
997 res = window->res; in pci_register_host_bridge()
998 if (!res->flags && !res->start && !res->end) { in pci_register_host_bridge()
1004 list_move_tail(&window->node, &bridge->windows); in pci_register_host_bridge()
1006 if (res->flags & IORESOURCE_BUS) in pci_register_host_bridge()
1007 pci_bus_insert_busn_res(bus, bus->number, res->end); in pci_register_host_bridge()
1013 fmt = " (bus address [%#06llx-%#06llx])"; in pci_register_host_bridge()
1015 fmt = " (bus address [%#010llx-%#010llx])"; in pci_register_host_bridge()
1018 (unsigned long long)(res->start - offset), in pci_register_host_bridge()
1019 (unsigned long long)(res->end - offset)); in pci_register_host_bridge()
1023 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); in pci_register_host_bridge()
1027 list_add_tail(&bus->node, &pci_root_buses); in pci_register_host_bridge()
1033 put_device(&bridge->dev); in pci_register_host_bridge()
1034 device_del(&bridge->dev); in pci_register_host_bridge()
1053 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_bridge_child_ext_cfg_accessible()
1069 * - PCI-to-PCI bridges in pci_bridge_child_ext_cfg_accessible()
1070 * - PCIe-to-PCI/PCI-X forward bridges in pci_bridge_child_ext_cfg_accessible()
1071 * - PCI/PCI-X-to-PCIe reverse bridges in pci_bridge_child_ext_cfg_accessible()
1073 * if the bridge supports PCI-X Mode 2. in pci_bridge_child_ext_cfg_accessible()
1096 child->parent = parent; in pci_alloc_child_bus()
1097 child->sysdata = parent->sysdata; in pci_alloc_child_bus()
1098 child->bus_flags = parent->bus_flags; in pci_alloc_child_bus()
1101 if (host->child_ops) in pci_alloc_child_bus()
1102 child->ops = host->child_ops; in pci_alloc_child_bus()
1104 child->ops = parent->ops; in pci_alloc_child_bus()
1110 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
1111 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
1114 child->number = child->busn_res.start = busnr; in pci_alloc_child_bus()
1115 child->primary = parent->busn_res.start; in pci_alloc_child_bus()
1116 child->busn_res.end = 0xff; in pci_alloc_child_bus()
1119 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
1123 child->self = bridge; in pci_alloc_child_bus()
1124 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
1125 child->dev.parent = child->bridge; in pci_alloc_child_bus()
1135 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; in pci_alloc_child_bus()
1141 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; in pci_alloc_child_bus()
1142 child->resource[i]->name = child->name; in pci_alloc_child_bus()
1144 bridge->subordinate = child; in pci_alloc_child_bus()
1148 ret = device_register(&child->dev); in pci_alloc_child_bus()
1153 if (child->ops->add_bus) { in pci_alloc_child_bus()
1154 ret = child->ops->add_bus(child); in pci_alloc_child_bus()
1156 dev_err(&child->dev, "failed to add bus: %d\n", ret); in pci_alloc_child_bus()
1173 list_add_tail(&child->node, &parent->children); in pci_add_new_bus()
1194 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1210 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) in pci_ea_fixed_busnrs()
1231 * pci_scan_bridge_extend() - Scan buses behind a bridge
1238 * distributed equally between hotplug-capable bridges.
1246 * We need to process bridges in two passes -- first we scan those
1258 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge_extend()
1271 pm_runtime_get_sync(&dev->dev); in pci_scan_bridge_extend()
1278 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge_extend()
1281 if (!primary && (primary != bus->number) && secondary && subordinate) { in pci_scan_bridge_extend()
1283 primary = bus->number; in pci_scan_bridge_extend()
1288 (primary != bus->number || secondary <= bus->number || in pci_scan_bridge_extend()
1290 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge_extend()
1296 * Disable Master-Abort Mode during probing to avoid reporting of in pci_scan_bridge_extend()
1327 child->primary = primary; in pci_scan_bridge_extend()
1329 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1332 buses = subordinate - secondary; in pci_scan_bridge_extend()
1338 /* Subordinate should equal child->busn_res.end */ in pci_scan_bridge_extend()
1375 * This can happen when a bridge is hot-plugged, so in this in pci_scan_bridge_extend()
1376 * case we only re-scan this bus. in pci_scan_bridge_extend()
1384 bus->busn_res.end); in pci_scan_bridge_extend()
1388 available_buses--; in pci_scan_bridge_extend()
1391 | ((unsigned int)(child->primary) << 0) in pci_scan_bridge_extend()
1392 | ((unsigned int)(child->busn_res.start) << 8) in pci_scan_bridge_extend()
1393 | ((unsigned int)(child->busn_res.end) << 16); in pci_scan_bridge_extend()
1408 child->bridge_ctl = bctl; in pci_scan_bridge_extend()
1414 * cards with a PCI-to-PCI bridge can be inserted in pci_scan_bridge_extend()
1422 while (parent->parent) { in pci_scan_bridge_extend()
1424 (parent->busn_res.end > max) && in pci_scan_bridge_extend()
1425 (parent->busn_res.end <= max+i)) { in pci_scan_bridge_extend()
1428 parent = parent->parent; in pci_scan_bridge_extend()
1434 * bridges -- try to leave one in pci_scan_bridge_extend()
1455 sprintf(child->name, in pci_scan_bridge_extend()
1457 pci_domain_nr(bus), child->number); in pci_scan_bridge_extend()
1460 while (bus->parent) { in pci_scan_bridge_extend()
1461 if ((child->busn_res.end > bus->busn_res.end) || in pci_scan_bridge_extend()
1462 (child->number > bus->busn_res.end) || in pci_scan_bridge_extend()
1463 (child->number < bus->number) || in pci_scan_bridge_extend()
1464 (child->busn_res.end < bus->number)) { in pci_scan_bridge_extend()
1465 …dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", in pci_scan_bridge_extend()
1466 &child->busn_res); in pci_scan_bridge_extend()
1469 bus = bus->parent; in pci_scan_bridge_extend()
1475 pm_runtime_put(&dev->dev); in pci_scan_bridge_extend()
1481 * pci_scan_bridge() - Scan buses behind a bridge
1492 * We need to process bridges in two passes -- first we scan those
1507 * The architecture-dependent code can tweak these, of course.
1514 if (dev->is_virtfn) { in pci_read_irq()
1515 dev->pin = 0; in pci_read_irq()
1516 dev->irq = 0; in pci_read_irq()
1521 dev->pin = irq; in pci_read_irq()
1524 dev->irq = irq; in pci_read_irq()
1539 pdev->pcie_cap = pos; in set_pcie_port_type()
1541 pdev->pcie_flags_reg = reg16; in set_pcie_port_type()
1542 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); in set_pcie_port_type()
1543 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); in set_pcie_port_type()
1547 pdev->link_active_reporting = 1; in set_pcie_port_type()
1567 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1568 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; in set_pcie_port_type()
1578 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; in set_pcie_port_type()
1579 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; in set_pcie_port_type()
1590 pdev->is_hotplug_bridge = 1; in set_pcie_hotplug_bridge()
1600 dev->is_thunderbolt = 1; in set_pcie_thunderbolt()
1613 if (parent->untrusted) { in set_pcie_untrusted()
1614 dev->untrusted = true; in set_pcie_untrusted()
1620 dev->untrusted = true; in set_pcie_untrusted()
1641 if (dev_is_removable(&parent->dev)) { in pci_set_removable()
1642 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); in pci_set_removable()
1648 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); in pci_set_removable()
1653 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1656 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1665 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1690 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1693 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1721 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to in pci_cfg_space_size()
1725 * the fact that the SR-IOV capability on the PF resides in extended in pci_cfg_space_size()
1726 * config space and must be accessible and non-aliased to have enabled in pci_cfg_space_size()
1730 if (dev->is_virtfn) in pci_cfg_space_size()
1734 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) in pci_cfg_space_size()
1737 class = dev->class >> 8; in pci_cfg_space_size()
1760 if (dev->is_virtfn) in pci_class()
1761 return dev->physfn->sriov->class; in pci_class()
1770 if (dev->is_virtfn) { in pci_subsystem_ids()
1771 *vendor = dev->physfn->sriov->subsystem_vendor; in pci_subsystem_ids()
1772 *device = dev->physfn->sriov->subsystem_device; in pci_subsystem_ids()
1785 if (dev->is_virtfn) in pci_hdr_type()
1786 return dev->physfn->sriov->hdr_type; in pci_hdr_type()
1795 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1799 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1813 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI in pci_intx_mask_broken()
1837 * pci_setup_device - Fill in class and map information of a device
1841 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1857 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1858 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1859 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1860 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1861 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1862 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1873 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) in pci_setup_device()
1876 dev->dma_mask = 0xffffffff; in pci_setup_device()
1878 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1879 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1880 PCI_FUNC(dev->devfn)); in pci_setup_device()
1884 dev->revision = class & 0xff; in pci_setup_device()
1885 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1890 /* Need to have dev->class ready */ in pci_setup_device()
1891 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1893 /* Need to have dev->cfg_size ready */ in pci_setup_device()
1899 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1907 dev->vendor, dev->device, dev->hdr_type, dev->class); in pci_setup_device()
1910 class = dev->class >> 8; in pci_setup_device()
1912 if (dev->non_compliant_bars && !dev->mmio_always_on) { in pci_setup_device()
1915 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1922 dev->broken_intx_masking = pci_intx_mask_broken(dev); in pci_setup_device()
1924 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1931 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); in pci_setup_device()
1936 * addresses. These are not always echoed in BAR0-3, and in pci_setup_device()
1937 * BAR0-3 in a few cases contain junk! in pci_setup_device()
1945 res = &dev->resource[0]; in pci_setup_device()
1946 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1947 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1952 res = &dev->resource[1]; in pci_setup_device()
1953 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1954 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1961 res = &dev->resource[2]; in pci_setup_device()
1962 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1963 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1968 res = &dev->resource[3]; in pci_setup_device()
1969 res->flags = LEGACY_IO_RESOURCE; in pci_setup_device()
1970 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1979 * The PCI-to-PCI bridge spec requires that subtractive in pci_setup_device()
1984 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
1990 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1991 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
2000 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
2001 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
2006 dev->hdr_type); in pci_setup_device()
2008 return -EIO; in pci_setup_device()
2012 dev->class, dev->hdr_type); in pci_setup_device()
2013 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
2028 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ in pci_configure_mps()
2029 if (dev->is_virtfn) in pci_configure_mps()
2040 mps = 128 << dev->pcie_mpss; in pci_configure_mps()
2071 mpss = 128 << dev->pcie_mpss; in pci_configure_mps()
2075 mpss, p_mps, 128 << bridge->pcie_mpss); in pci_configure_mps()
2111 host = pci_find_host_bridge(dev->bus); in pci_configure_extended_tags()
2119 if (host->no_ext_tags) { in pci_configure_extended_tags()
2137 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2157 if (dev->is_virtfn) in pci_configure_relaxed_ordering()
2165 * Ports. Peer-to-Peer DMA is another can of worms. in pci_configure_relaxed_ordering()
2171 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { in pci_configure_relaxed_ordering()
2181 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); in pci_configure_ltr()
2189 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); in pci_configure_ltr()
2198 dev->ltr_path = 1; in pci_configure_ltr()
2203 if (bridge && bridge->ltr_path) in pci_configure_ltr()
2204 dev->ltr_path = 1; in pci_configure_ltr()
2209 if (!host->native_ltr) in pci_configure_ltr()
2220 dev->ltr_path = 1; in pci_configure_ltr()
2225 * If we're configuring a hot-added device, LTR was likely in pci_configure_ltr()
2226 * disabled in the upstream bridge, so re-enable it before enabling in pci_configure_ltr()
2230 if (bridge && bridge->ltr_path) { in pci_configure_ltr()
2234 dev->ltr_path = 1; in pci_configure_ltr()
2256 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2259 if (bridge && bridge->eetlp_prefix_path) in pci_configure_eetlp_prefix()
2260 dev->eetlp_prefix_path = 1; in pci_configure_eetlp_prefix()
2269 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_configure_serr()
2304 * pci_release_dev - Free a PCI device structure when all users of it are
2319 pci_bus_put(pci_dev->bus); in pci_release_dev()
2320 kfree(pci_dev->driver_override); in pci_release_dev()
2321 bitmap_free(pci_dev->dma_alias_mask); in pci_release_dev()
2334 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
2335 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
2336 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
2337 dev->driver_exclusive_resource = (struct resource) { in pci_alloc_dev()
2340 .end = -1, in pci_alloc_dev()
2343 spin_lock_init(&dev->pcie_cap_lock); in pci_alloc_dev()
2345 raw_spin_lock_init(&dev->msi_lock); in pci_alloc_dev()
2375 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2376 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2382 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2383 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2394 pci_domain_nr(bus), bus->number, in pci_bus_wait_crs()
2395 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); in pci_bus_wait_crs()
2421 struct pci_dev *bridge = bus->self; in pci_bus_read_dev_vendor_id()
2427 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && in pci_bus_read_dev_vendor_id()
2428 bridge->device == 0x80b5) in pci_bus_read_dev_vendor_id()
2437 * Read the config data for a PCI device, sanity-check it,
2452 dev->devfn = devfn; in pci_scan_device()
2453 dev->vendor = l & 0xffff; in pci_scan_device()
2454 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
2457 pci_bus_put(dev->bus); in pci_scan_device()
2476 /* Multi-function PCIe devices share the same link/status */ in pcie_report_downtraining()
2477 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) in pcie_report_downtraining()
2488 pci_msix_init(dev); /* Disable MSI-X */ in pci_init_capabilities()
2490 /* Buffers for saving PCIe and PCI-X capabilities */ in pci_init_capabilities()
2495 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ in pci_init_capabilities()
2514 * per-device basis should be called from here.
2524 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
2544 * If the platform or firmware interfaces cannot supply a in pci_set_msi_domain()
2545 * device-specific MSI domain, then inherit the default domain in pci_set_msi_domain()
2550 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
2552 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
2561 device_initialize(&dev->dev); in pci_device_add()
2562 dev->dev.release = pci_release_dev; in pci_device_add()
2564 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
2565 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
2566 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
2567 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
2569 dma_set_max_seg_size(&dev->dev, 65536); in pci_device_add()
2570 dma_set_seg_boundary(&dev->dev, 0xffffffff); in pci_device_add()
2579 dev->state_saved = false; in pci_device_add()
2588 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
2598 dev->match_driver = false; in pci_device_add()
2599 ret = device_add(&dev->dev); in pci_device_add()
2630 return -ENODEV; in next_ari_fn()
2634 return -ENODEV; in next_ari_fn()
2639 return -ENODEV; /* protect against malformed list */ in next_ari_fn()
2650 return -ENODEV; in next_fn()
2652 if (dev && !dev->multifunction) in next_fn()
2653 return -ENODEV; in next_fn()
2660 struct pci_dev *bridge = bus->self; in only_one_child()
2681 * pci_scan_slot - Scan a PCI slot on a bus for devices
2686 * discovered devices to the @bus->devices list. New devices
2705 dev->multifunction = 1; in pci_scan_slot()
2719 if (bus->self && nr) in pci_scan_slot()
2720 pcie_aspm_init_link_state(bus->self); in pci_scan_slot()
2735 * drivers attached. A hot-added device might support only the minimum in pcie_find_smpss()
2737 * where devices may be hot-added, we limit the fabric MPS to 128 so in pcie_find_smpss()
2738 * hot-added devices will work correctly. in pcie_find_smpss()
2740 * However, if we hot-add a device to a slot directly below a Root in pcie_find_smpss()
2743 * reconfigure MPS on both the Root Port and the hot-added device, in pcie_find_smpss()
2746 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. in pcie_find_smpss()
2748 if (dev->is_hotplug_bridge && in pcie_find_smpss()
2752 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
2753 *smpss = dev->pcie_mpss; in pcie_find_smpss()
2763 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
2766 dev->bus->self) in pcie_write_mps()
2781 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
2845 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
2852 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2860 if (!bus->self) in pcie_bus_configure_settings()
2863 if (!pci_is_pcie(bus->self)) in pcie_bus_configure_settings()
2867 * FIXME - Peer to peer DMA is possible, though the endpoint would need in pcie_bus_configure_settings()
2875 smpss = bus->self->pcie_mpss; in pcie_bus_configure_settings()
2877 pcie_find_smpss(bus->self, &smpss); in pcie_bus_configure_settings()
2881 pcie_bus_configure_set(bus->self, &smpss); in pcie_bus_configure_settings()
2896 * pci_scan_child_bus_extend() - Scan devices below a bus
2904 * equally between hotplug-capable bridges to allow future extension of the
2911 unsigned int start = bus->busn_res.start; in pci_scan_child_bus_extend()
2915 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus_extend()
2921 /* Reserve buses for SR-IOV capability */ in pci_scan_child_bus_extend()
2926 * After performing arch-dependent fixup of the bus, look behind in pci_scan_child_bus_extend()
2927 * all PCI-to-PCI bridges on this bus. in pci_scan_child_bus_extend()
2929 if (!bus->is_added) { in pci_scan_child_bus_extend()
2930 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus_extend()
2932 bus->is_added = 1; in pci_scan_child_bus_extend()
2941 if (dev->is_hotplug_bridge) in pci_scan_child_bus_extend()
2961 if (max - cmax > 1) in pci_scan_child_bus_extend()
2962 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
2977 } else if (dev->is_hotplug_bridge) { in pci_scan_child_bus_extend()
2983 buses = min(buses, available_buses - used_buses + 1); in pci_scan_child_bus_extend()
2989 if (max - cmax > 1) in pci_scan_child_bus_extend()
2990 used_buses += max - cmax - 1; in pci_scan_child_bus_extend()
2998 if (bus->self && bus->self->is_hotplug_bridge) { in pci_scan_child_bus_extend()
3000 pci_hotplug_bus_size - 1); in pci_scan_child_bus_extend()
3001 if (max - start < used_buses) { in pci_scan_child_bus_extend()
3005 if (max > bus->busn_res.end) in pci_scan_child_bus_extend()
3006 max = bus->busn_res.end; in pci_scan_child_bus_extend()
3008 dev_dbg(&bus->dev, "%pR extended by %#02x\n", in pci_scan_child_bus_extend()
3009 &bus->busn_res, max - start); in pci_scan_child_bus_extend()
3018 * Return how far we've got finding sub-buses. in pci_scan_child_bus_extend()
3020 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus_extend()
3025 * pci_scan_child_bus() - Scan devices below a bus
3038 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3041 * Default empty implementation. Replace with an architecture-specific setup
3067 bridge->dev.parent = parent; in pci_create_root_bus()
3069 list_splice_init(resources, &bridge->windows); in pci_create_root_bus()
3070 bridge->sysdata = sysdata; in pci_create_root_bus()
3071 bridge->busnr = bus; in pci_create_root_bus()
3072 bridge->ops = ops; in pci_create_root_bus()
3078 return bridge->bus; in pci_create_root_bus()
3081 put_device(&bridge->dev); in pci_create_root_bus()
3093 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in pci_host_probe()
3097 bus = bridge->bus; in pci_host_probe()
3110 list_for_each_entry(child, &bus->children, node) in pci_host_probe()
3121 struct resource *res = &b->busn_res; in pci_bus_insert_busn_res()
3124 res->start = bus; in pci_bus_insert_busn_res()
3125 res->end = bus_max; in pci_bus_insert_busn_res()
3126 res->flags = IORESOURCE_BUS; in pci_bus_insert_busn_res()
3129 parent_res = &b->parent->busn_res; in pci_bus_insert_busn_res()
3132 res->flags |= IORESOURCE_PCI_FIXED; in pci_bus_insert_busn_res()
3138 dev_info(&b->dev, in pci_bus_insert_busn_res()
3141 parent_res, conflict->name, conflict); in pci_bus_insert_busn_res()
3148 struct resource *res = &b->busn_res; in pci_bus_update_busn_res_end()
3153 if (res->start > bus_max) in pci_bus_update_busn_res_end()
3154 return -EINVAL; in pci_bus_update_busn_res_end()
3156 size = bus_max - res->start + 1; in pci_bus_update_busn_res_end()
3157 ret = adjust_resource(res, res->start, size); in pci_bus_update_busn_res_end()
3158 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", in pci_bus_update_busn_res_end()
3161 if (!ret && !res->parent) in pci_bus_update_busn_res_end()
3162 pci_bus_insert_busn_res(b, res->start, res->end); in pci_bus_update_busn_res_end()
3169 struct resource *res = &b->busn_res; in pci_bus_release_busn_res()
3172 if (!res->flags || !res->parent) in pci_bus_release_busn_res()
3176 dev_info(&b->dev, "busn_res: %pR %s released\n", in pci_bus_release_busn_res()
3188 return -EINVAL; in pci_scan_root_bus_bridge()
3190 resource_list_for_each_entry(window, &bridge->windows) in pci_scan_root_bus_bridge()
3191 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus_bridge()
3192 bridge->busnr = window->res->start; in pci_scan_root_bus_bridge()
3201 b = bridge->bus; in pci_scan_root_bus_bridge()
3202 bus = bridge->busnr; in pci_scan_root_bus_bridge()
3205 dev_info(&b->dev, in pci_scan_root_bus_bridge()
3206 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus_bridge()
3229 if (window->res->flags & IORESOURCE_BUS) { in pci_scan_root_bus()
3239 dev_info(&b->dev, in pci_scan_root_bus()
3240 "No busn resource found for root bus, will use [bus %02x-ff]\n", in pci_scan_root_bus()
3274 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3287 struct pci_bus *bus = bridge->subordinate; in pci_rescan_bus_bridge_resize()
3299 * pci_rescan_bus - Scan a PCI bus for devices
3343 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; in pci_sort_bf_cmp()
3344 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; in pci_sort_bf_cmp()
3346 if (a->bus->number < b->bus->number) return -1; in pci_sort_bf_cmp()
3347 else if (a->bus->number > b->bus->number) return 1; in pci_sort_bf_cmp()
3349 if (a->devfn < b->devfn) return -1; in pci_sort_bf_cmp()
3350 else if (a->devfn > b->devfn) return 1; in pci_sort_bf_cmp()
3362 struct pci_bus *parent = dev->bus; in pci_hp_add_bridge()
3363 int busnr, start = parent->busn_res.start; in pci_hp_add_bridge()
3365 int end = parent->busn_res.end; in pci_hp_add_bridge()
3371 if (busnr-- > end) { in pci_hp_add_bridge()
3372 pci_err(dev, "No bus number available for hot-added bridge\n"); in pci_hp_add_bridge()
3373 return -1; in pci_hp_add_bridge()
3380 * Distribute the available bus numbers between hotplug-capable in pci_hp_add_bridge()
3383 available_buses = end - busnr; in pci_hp_add_bridge()
3388 if (!dev->subordinate) in pci_hp_add_bridge()
3389 return -1; in pci_hp_add_bridge()