31 #define ASPM_STATE_L0S_DW	(2)	/* Downstream direction L0s state */
47 	struct pci_dev *downstream;	/* Downstream component, function 0 */  member
212 	/* Check downstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
242 	/* Configure downstream component, all functions */  in pcie_aspm_configure_common_clock()
399 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
441 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_calc_l12_info()
471 	 * downstream devices report (via LTR) that they can tolerate at  in aspm_calc_l12_info()
529 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_l1ss_init()
586 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_aspm_cap_init()
611 	 * Re-read upstream/downstream components' register state after  in pcie_aspm_cap_init()
665 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_l1ss()
724 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_link()
743 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
759 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
831 	link->downstream = pci_function_0(pdev->subordinate);  in alloc_pcie_link_state()
836 	 * the root ports entirely, in which case a downstream port on  in alloc_pcie_link_state()
873  * @pdev: the root port or switch downstream port
889 	 * downstream port.  in pcie_aspm_init_link_state()
980 	 * link->downstream is a pointer to the pci_dev of function 0.  If  in pcie_aspm_exit_link_state()
982 	 * so we can't use link->downstream again.  Free the link state to  in pcie_aspm_exit_link_state()
1005  * @pdev: the root port or switch downstream port