50 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {  variable
358 	bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,  in pci_bridge_emul_init()
359 					    sizeof(pci_regs_behavior),  in pci_bridge_emul_init()
361 	if (!bridge->pci_regs_behavior)  in pci_bridge_emul_init()
397 			kfree(bridge->pci_regs_behavior);  in pci_bridge_emul_init()
401 		bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=  in pci_bridge_emul_init()
403 		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=  in pci_bridge_emul_init()
409 		bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=  in pci_bridge_emul_init()
411 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=  in pci_bridge_emul_init()
414 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=  in pci_bridge_emul_init()
417 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=  in pci_bridge_emul_init()
419 		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=  in pci_bridge_emul_init()
424 		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;  in pci_bridge_emul_init()
425 		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;  in pci_bridge_emul_init()
429 		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;  in pci_bridge_emul_init()
430 		bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;  in pci_bridge_emul_init()
431 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);  in pci_bridge_emul_init()
432 		bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);  in pci_bridge_emul_init()
433 		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;  in pci_bridge_emul_init()
434 		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;  in pci_bridge_emul_init()
449 	kfree(bridge->pci_regs_behavior);  in pci_bridge_emul_cleanup()
472 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_read()
553 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_write()