139 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&  in pcie_wait_cmd()
140 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)  in pcie_wait_cmd()
147 			  ctrl->slot_ctrl,  in pcie_wait_cmd()
160 	u16 slot_ctrl_orig, slot_ctrl;  in pcie_do_write_cmd()  local
169 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pcie_do_write_cmd()
170 	if (PCI_POSSIBLE_ERROR(slot_ctrl)) {  in pcie_do_write_cmd()
175 	slot_ctrl_orig = slot_ctrl;  in pcie_do_write_cmd()
176 	slot_ctrl &= ~mask;  in pcie_do_write_cmd()
177 	slot_ctrl |= (cmd & mask);  in pcie_do_write_cmd()
180 	ctrl->slot_ctrl = slot_ctrl;  in pcie_do_write_cmd()
181 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);  in pcie_do_write_cmd()
192 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))  in pcie_do_write_cmd()
353 	u16 slot_ctrl;  in pciehp_get_raw_indicator_status()  local
356 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_raw_indicator_status()
358 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;  in pciehp_get_raw_indicator_status()
366 	u16 slot_ctrl;  in pciehp_get_attention_status()  local
369 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_attention_status()
372 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_attention_status()
374 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {  in pciehp_get_attention_status()
395 	u16 slot_ctrl;  in pciehp_get_power_status()  local
397 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_power_status()
399 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_power_status()
401 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {  in pciehp_get_power_status()
600 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))  in pciehp_isr()